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With decreasing size of transistors, the impact oftransient faults as well as the local and global variability of transistors increases, affecting system functions and performances. Formal verification may be used to prove that a circuit isrobust against transient and parametric faults. However, a modelincluding timing information combined with extracted electricalparameters is typically too large...
This paper devotes to a new 5-2 compressor designed according to a new architecture with a pure Glitchless output. A considerable increase in the speed of the operation is achieved by utilizing a new truth table, fast production of signals Cout1 and Cout2, optimum tuning of the width of the utilizing transistors, and eliminating the parasitic capacitances through merging the drain of transistors....
This paper, presents a new design for 1-bit full adder cell using hybrid-CMOS logic style. The new full adder is based on a novel XOR-XNOR circuit that generates XOR and XNOR full-swing outputs simultaneously and outperforms its best counterpart showing 43% improvement in power-delay product (PDP). The proposed full adder provides full-swing output with good driving capability and it is a proper choice...
This paper presents a new structure of 1-bit full adder for sub-threshold technology. It compares full adder sub-circuits and also compares the proposed full adder with common full adders in terms of propagation delay, power consumption, power delay product and square power delay product in sub-threshold technology. HSPICE simulations show that the power dissipation, power delay product and square...
Delay estimation is considered as one of the critical issues in the development of any Very Large Scale Integration (VLSI) design algorithms. It is also known as one of the factors to analyze in the design of high performance integrated circuit. Neither of these is usually applied to observe the performance of various VLSI topologies. High performance integrated circuits often use adders to achieve...
This paper devotes to a new 7-2 compressor designed according to a new architecture with a pure Glitchless output. A considerable increase in the speed of the operation is achieved by utilizing a new truth table, fast production of signals Cout1 and Cout2, optimum tuning of the width of the utilizing transistors, and eliminating the parasitic capacitances through merging the drain of transistors....
Analysis of the operation of CMOS gates is a complicated procedure. These gates can be replaced by equivalent inverters and therefore the expressions for the inverters are used to determine the electrical characteristics of the gates. In this paper, the equivalent inverter approach for replacing CMOS gates is evaluated. The NAND gate is used for this evaluation. Parametric expressions are created...
Based on the existing voltage balancing scheme for two series HV-IGBTs (High voltage insulated gate bipolar transistors) with active clamping and status feedback, this paper focuses on the characteristics of IGBT with active clamping circuit. First, the previous series IGBT model is improved according to the experiment results in order to give accurate feedback signal in the active clamping sub-circuit...
In today's electricity market, the power supply enterprises have to face power quality problems. The reducing of power system frequency threaten the safety of power grids. At this time, we have to use the Under Frequency Load Shedding(Hereinafter referred to as the UFLS) device to remove partial load, to restore the system frequency within the level of security. UFLS device, therefore, the correct...
The use of fine-grain Dynamic Voltage and Frequency Scaling (DVFS) has increased the number of distinct clock domains on a given Network-on-Chip (NoC). This necessitates robust synchronizers to prevent clock domain communication failures, even as FinFET devices have begun to replace planar devices. This paper presents simulation results and comparisons between dynamic (requiring reset) and non-dynamic...
Compressors play a significant role in overall performance of multipliers and hence in efficiency of arithmetic circuits. To further improvement of multipliers higher order compressors have been considered. In this paper, two novel 5:2 compressors are presented. The proposed architectures lay emphasis on the idea of making the carry-out signal Cout2 independent of Cin1. Therefore, we have developed...
This paper introduces a new joint probability density function (JPDF) for estimating delay-power distribution. Linear and logarithmic skewness factors have been used for estimating the accurate JPDF. Both proposed models are compared to bivariate normal model for NAND2, NAND3, NOR2, NOR3 circuits and ISCAS85-C432We verified the accuracy of our proposed model using Nangate 45nm standard cell library...
A method of serial links output data and clock signals setup and hold times correction presented in this paper. The proposed architecture produces corrected clock which have enough setup/hold time margins respect data signal over PVT, which is needed to avoid data errors and setup/hold violations during further operation with data. The presented correction mechanism can be used in the special input/output...
Delay testing has become a major issue for manufacturing advanced Systems on a Chip. Automatic Test Equipment and scan techniques are usually applied in delay testing. However, the circuits under test have many circuit paths and dependent input patterns; it is hard to measure delay times accurately, especially when debugging small delay defects. We propose a Built-In Delay Measurement (BIDM) circuit...
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