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In this paper, an adiabatic based vernier time-to-digital converter (VTDC) is proposed. Generally, static based vernier TDC consumes more power due to two delay chain and D-flipflop. To avoid this issue an adiabatic based vernier TDC is proposed. This proposed TDC is constructed by using adiabatic inverter and D-flipflop but in classical TDC architecture consists of static based inverter and D-flipflop...
High-speed phase frequency detector (PFD) is one of the key module for high-frequency phase locked loop (PLL) systems. The performance of PLL depends on the operation of PFD. This paper presents a new PFD design in 0.18μm CMOS technology using 3T XOR and 3T NAND gates. Supply voltage has been varied from 1.8V to 2.4V in the proposed design. The new PFD consumes power within a range from 505.78μW to...
A new nonlinear Time to Digital Converter (TDC) based on time difference amplification is the proposed. A new gain compensation method is presented to expand the DR of conventional ×2 Time Amplifiers (TAs). Instead of conventional gain compensation approach based on changing strength of current sources, the proposed technique uses current difference which results more stable gain over wider DR. In...
This paper presents a high resolution tunable ring oscillator type TDC (Time to Digital Converter). The proposed structure uses 2 ring oscillators composed of 8 differential inverters. Can be activated by selecting one of the three resolution in the structure, and can be selected in a ratio of 15/16, 13/32, 63/64, depending on fast and slow of the differential inverter delay. Also to increase the...
This paper presents a type-I digital ring-based PLL with wide loop bandwidth to lower the ring oscillator's noise contribution. The in-band noise is addressed using a SAR-ADC-based sampling phase detector (SPD). A stacked reference buffer is also introduced to reduce the transient short-circuit current for low power and low reference spur. The loop delay due to the D flip-flops at filter's output...
The most challenging issue of conventional Time Amplifiers (TAs) is their limited Dynamic Range (DR). This paper presents a mathematical analysis to clarify principle of operation of conventional 2× TA's. The mathematical derivations release strength reduction of the current sources of the TA is the simplest way to increase DR. Besides, a new technique is presented to expand the Dynamic Range (DR)...
One decade after their introduction into wireless applications, digital fractional-N phase-locked loops are becoming a competitive solution for products. Their ultimate level of spurs is often bounded by the resolution and the linearity of the time-to-digital converter. Although methods for mitigating its nonlinearity have been proven effective in lowering spurs, they typically increase the level...
This paper introduces a technique for suppressing the effect of deterministic jitter in phase-locked loops based on multiplying delay-locked loops. A digital loop operating in background of normal operation detects the static phase offset between the two reference-signal paths by means of a single-bit time-to-digital converter and compensates for it by means of a digital-to-time converter.
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