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This paper presents a new approach for generating saturation constraints and DC performance expressions for analog integrated circuits. It also proposes a generalized method to develop AC performance expressions of the same in posynomial form. The developed posynomial expressions can be used for well established geometric programming (GP) based sizing optimization. The equation generation method takes...
New analytical equations are proposed for oscillation amplitude of the MOS Colpitts oscillator. These equations are obtained from a large signal analysis. The analysis is based on a reasonable estimation for the output waveform. The estimated waveform should satisfy the nonlinear differential equations governing the circuit. The validity of the resulted equations is verified through simulations using...
An original multifunctional structure with improved performances will be presented. The great advantages of increased modularity, controllability and of the associated reduced design costs represent an immediate consequence of multiple functions that could be implemented by the proposed structure: amplifying, multiplying, squaring or simulating positive and negative resistances. The circuit accuracy...
A step-by-step design procedure of sub-bandgap voltage reference (BGR) is proposed. The procedure shows on example structure main design steps of crucial parameters verified later by a simulation. The block is meant to be fabricated in 0.35 μm CMOS process with analog options. The main features of the concept are the sub-bandgap output voltage of 0.7 V, low supply voltage from 1.3 V, low power consumption...
Electronics submicrometrics devices present large systematic parameter variations related to imperfections during the fabrication process. These variations impact directly on the analog design, causing low reliability and increasing costs. This work presents a sensitivity analysis of parameter variation for a typical CMOS two-stage Miller operational transconductance amplifier, analyzing the main...
Recently a new CMOS current-mode pseudo-exponential function generator circuit was reported by Popa. The entire analysis and exponential function generator circuit, given in Popa's paper, is based on a current-squaring circuit module. In this comment paper we show that the current-squarer circuit, presented in Popa's paper, does not work as a current squarer. Consequently the pseudo-exponential generator...
Noise performance of the switched source follower (SSF) track and hold (T/H) circuit is analyzed. Approximate expressions for the output noise of the track mode and hold mode of the T/H circuit are derived respectively. Simulations based on a commercial available 65 nm process technology are implemented with the SpectreRF circuit simulator. It is shown that the noise contribution from the parasitic...
Geometric programming (GP) has been employed in automatic design of analog integrated circuits. Its major advantage is the ability to find the globally optimum solution to a problem. It however, suffers from dependency on the accuracy of the initial equations and the parameters used in these equations. This, in circuit design, causes discrepancies between GP predictions and simulation results-especially...
A wide input voltage range differential difference operational floating amplifier is introduced. The proposed realization is based on the cascading connection of a differential difference transconductor (DDT) and a differential input balanced output current op-amp (DIBO). The proposed DDT is based on differential transconductor stage with rail-to-rail differential input voltage swing. The DIBO current...
While the CMOS analog circuits can be designed with the minimum-gate-length of the fabrication process in the alpha-power law MOSFET model, the length of a MOSFET gate has been chosen to be a larger scale than the minimum-gate-length in the conventional Shockleypsilas square model. In this paper, we describe a 6-b 100 MSPS CMOS current steering digital-to-analog converter (DAC) with the alpha-power...
In this paper we propose a four-quadrant multiplier based on a core cell that exploits the relationship between the saturation current of an MOS transistor and the source transconductance. The advantages of the proposed topology are simplicity and feasibility of low-power and low-voltage operation. Experimental results in a 0.35 mum CMOS prototype indicate 1 mA consumption for 1 MHz bandwidth, and...
This work is concerned with the design automation of analog circuits realizing piecewise linear functions (PWL) that may be used for fuzzy logic circuit design. There are several sources of systematic or random errors in the design of such functions. Various combinations of CMOS current mirror circuits are used to implement PWL functions. In order to simplify the optimization of implementation, PWL...
The computer-aided design (CAD) methodology proposed in this paper, automates analog static CMOS design. This methodology is based on the EKV model which is continuous over the inversion range. This methodology provides accurate description of current drain (error < 10%) with integration of second order effects in charts for simplicity. It explores the whole solution space. Thus, circuits are sized...
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