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This paper concerns a quarter-square analog four-quadrant multiplier, based on proprietary architecture using four CMOS inverters. The most important difference with respect to already published own circuit implementation is the use of inverter `core' of the circuit with completely redesigned auxiliary and steering blocks. The proposed circuit solution is suitable for RF applications in communication...
In this paper we propose a four-quadrant multiplier based on a core cell that exploits the relationship between the saturation current of an MOS transistor and the source transconductance. The advantages of the proposed topology are simplicity and feasibility of low-power and low-voltage operation. Experimental results in a 0.35 mum CMOS prototype indicate 1 mA consumption for 1 MHz bandwidth, and...
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