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Noise canceling techniques have been successfully applied to the design of modern multi-band RF-CMOS inductor-less receivers. However, low voltage supply requirements are imposing new design challenges which are pushing the operation of the MOS transistor into moderate or weak inversion, making the setup of closed sizing expressions a difficult task. This paper presents a Si2 OpenAccess based circuit...
In this paper it is presented a balun LNA, with voltage gain control that combines a common-gate and common-source stage, in which transistors biased in triode region replace the resistive loads. This last approach in conjunction with a dynamic threshold reduction technique allows a low supply voltage operation. Furthermore, a significant chip area reduction can be exploited by adopting an inductor-less...
This paper investigates the impact of high frequency noise correlation on SiGe HBT LNA design. With correlation, simultaneous noise and impedance match is found to continue to hold approximately. However, a larger size and hence a higher biasing current are required for noise matching. The actual noise figure (NF) of LNAs designed without considering noise correlation is also investigated. Further...
An accurate and simple noise de-embedding technique is proposed for high-frequency noise characterization of transistors. It is demonstrated on 0.13-μm CMOS devices for up to 80 GHz. The proposed technique adopts a generalized two-port fixture model in conjunction with a set of shielded based structures, which enable simple de-embedding of fixture parasitic for up to the Metal 1 level. Unlike other...
This paper presents the design of a MMIC oscillator operating at a 45 GHz frequency. This circuit was fabricated by Alcatel-Thales III-V Lab with the new InP/GaAsSb/InP DHBT submicronic technology (We=700 nm). This transistor has a 15-μm-long two-finger emitter. The complete nonlinear modeling of heterojunction bipolar transistor used in this circuit is described. The interest of the methodology used...
Indium antimonide (InSb) has the highest electron mobility and saturation velocity of any conventional semiconductor, giving potential for a range of analogue and digital ultra-high speed, low power dissipation applications. N-channel quantum well FETs have been fabricated with current gain cut-off frequency (fT) of 305 GHz and power gain cut-off frequency (fmax) of 480 GHz at VDS of only 0.5 V. Outline...
Probabilistic computing provides a new approach towards building fault-tolerant systems. In a fully digital system, the logic states are considered as random variables. One can no longer expect a correct logic signal at all nodes at all times, but only that the joint probability distribution of signal values has the highest likelihood for valid logic states. A case study on probabilistic architecture...
In this work, the bulk-gate controlled circuit to improve the power supply ripple ratio (PSRR) of a Low Dropout Regulator (LDO) which deteriorates due to lowering power consumption is proposed. Designing with 0.25 mum CMOS process, the simulation results by HSPICE shown that the proposed circuit provides a high performance of PSRR even though 1/10 of the power consumption is reduced compare to the...
This paper discusses the design of a 60 GHz low noise amplifier (LNA) using a standard low power SOI CMOS process from ST Microelectronics. First, we outline the technology as well as the mm-wave design challenges. Using recent work on coplanar waveguide (CPW) modeling, we describe how it's possible to use parametric, 3D electromagnetic simulation to complete or replace analytical models of on-chip...
Class D amplifiers are becoming the most feasible solution for embedded audio application. However, distortions due to the non-linear nature of switching stage are the main drawback for this amplifier topology. This paper discusses the design and implementation of high fidelity audio class D using sliding mode control scheme. This design method proves to be a cost effective solution for industrial...
In this paper a direct conversion mixer that adopts a passive mixing stage and achieves very good flicker noise performance is presented. The mixer achieves 7.4 dB of voltage conversion gain with a flicker noise corner frequency of 2 kHz and Third Order Input Intercept Point (IIP3) of 10 dBm. The circuit consumes only 4.5 mW from a 1 - V supply and it was implemented in a 90 nm CMOS RF technology.
The next generation of wireless communication is a ubiquitous radio system concept, providing wireless access from short-range to wide-area, with one single reconfigurable and adaptive system for all envisaged radio environments. This paper presents the design approach of RCO (reconfigurable concurrent oscillator) that simultaneously generates two or more signals of different frequencies that eliminate...
A high intercept points, cost-effective, and power-efficient switching FET double balanced mixer (DBM) is reported. The Switching FET DBM demonstrated in this work offers input intercept points (IIP3) and conversion loss typically 44 dBm and 8.5 dB respectively with 15 dBm LO power for the frequency band (RF: 900-2150 MHz, LO: 850-1950 MHz, IF: 50-200 MHz). The measured interport isolation is typically...
The transistors with large gate width are not really used by microwave circuit, because of the propagation phenomena problems and thermal dissipation (thermal noise). But the usefully frequencies becomes increasingly high, so the current short transistors will be affected by the propagation phenomena. This large width transistor noise analysis is fault of measurements limits beyond 18 GHz.
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