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In this paper, a new type of a 90nm CMOS LDO regulator with high load regulation using a gain goost-up technique. The development of low drop-out (LDO) regulator architectures in the power management family is necessary to reduce the standby power of portable applications such as cellular phones and PDAs. In essence, this LDO regulator suffers from an inherent load regulation which impedes to work...
A current buffer compensation Low Dropout (LDO) regulator for portable applications is present in this paper. The current buffer compensation scheme is a current feedback amplifier, which provides low output impendence in order to move the non-dominant pole due to the large gate capacitance of the pass transistor of the LDO regulator to high frequency. This LDO circuit had been designed and implemented...
A low-voltage, low-power, wide gain-range variable gain amplifier (VGA) design has been proposed. To provide wide gain range feature, the proposed VGA utilizes a novel pseudo-exponential function. The design synthesis is simplified and optimized using gm = ID method which enables us to characterize transistors in any operating region based on their gm = ID and VGS relation. As the result, in CMOS...
Fault simulation is one of the elemental steps in test pattern generation and is widely used for digital circuits. In case of analog circuits, fault simulation is not generally adopted because of the lack of suitable fault models and the time required for the transistor level simulation of the entire circuit. In this paper, a macromodel level fault model, which is able to represent the faulty behavior...
The implementation of complex functionality in low-power nano-CMOS technologies leads to enhance susceptibility to parametric disturbances (environmental, and operation-dependent). The purpose of this paper is to present recent improvements on a methodology to exploit power-supply voltage and temperature variations in order to produce fault-tolerant structural solutions. First, the proposed methodology...
Polymorphic gates can be considered as a new reconfigurable technology capable of integrating logic functions with sensing in a single compact structure. Polymorphic gates whose logic function can be controlled by the level of the power supply voltage (Vdd) represent a special class of polymorphic gates. A new polymorphic NAND/NOR gate controlled by Vdd is presented. This gate was fabricated and utilized...
The paper presents a detailed study on the idle leakage reduction techniques on partially depleted silicon-on-insulator (PD-SOI) CMOS SRAM. The most promising leakage reduction techniques that have been proposed are introduced, analyzed and compared into 65 nm low-power PD-SOI technology, taking into account all the SOI specific effect. Especially, it is shown that the leakage reduction techniques...
In this work, the bulk-gate controlled circuit to improve the power supply ripple ratio (PSRR) of a Low Dropout Regulator (LDO) which deteriorates due to lowering power consumption is proposed. Designing with 0.25 mum CMOS process, the simulation results by HSPICE shown that the proposed circuit provides a high performance of PSRR even though 1/10 of the power consumption is reduced compare to the...
Class D amplifiers are becoming the most feasible solution for embedded audio application. However, distortions due to the non-linear nature of switching stage are the main drawback for this amplifier topology. This paper discusses the design and implementation of high fidelity audio class D using sliding mode control scheme. This design method proves to be a cost effective solution for industrial...
Novel 3D stacked gate-all-around multichannel CMOS architectures were developed to propose low leakage solutions and new design opportunities for sub-32 nm nodes. Those architectures offer specific advantages compared to other planar or non planar CMOS devices. In particular, ultra-low IOFF (< 20 pA/mum) and high ION (> 2.2 mA/mum) were demonstrated. Moreover, those transistors do not suffer...
A new low-jitter polyphase-filter-based frequency multiplier incorporating a phase error calibration circuit to reduce the phase errors is presented. Designing with a multiplication ratio of eight, it has been fabricated in a 0.13-mum CMOS process. For input frequency of 25 MHz, the measured jitter is 2.46 ps (rms) and plusmn9.33 ps (pk-pk) at 200-MHz output frequency, while achievable maximum static...
A high intercept points, cost-effective, and power-efficient switching FET double balanced mixer (DBM) is reported. The Switching FET DBM demonstrated in this work offers input intercept points (IIP3) and conversion loss typically 44 dBm and 8.5 dB respectively with 15 dBm LO power for the frequency band (RF: 900-2150 MHz, LO: 850-1950 MHz, IF: 50-200 MHz). The measured interport isolation is typically...
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