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A new method of test generation based on the concept of partial test groups to prove the correctness of a combinational circuit is proposed. Stuck-at-faults (SAFs) of any multiplicity are assumed to be present in the circuit and we do not need to enumerate them. Unlike the known approaches, we do not target faults as test objectives. The goal is to verify by each test group the correctness of a selected...
This paper presents an enhanced path delay fault simulator for combinational circuits. The main objective of this work is to improve the simulation time of path delay fault testing. Our experiments consider K-longest path sets of ISCAS'85 benchmark circuits, and 10M single input change (SIC) test patterns were applied and repeated ten times in order to cover statistical variations. The experimental...
An effective test generation algorithm based on threshold for digital circuits is proposed in this paper. Firstly, threshold test generation model for digital circuit is constructed, acceptable faults can be distinguished from unacceptable faults by using the model. Then threshold test patterns can be generated for unacceptable faults by using mature stuck-at faults test generation algorithm. The...
Major proportion of the manufacturing cost of digital circuits is devoted to testing part. Reduction in the number of tests lowers the manufacturing cost and market price of digital circuits. The main focus of this research work is to minimize the number of tests performed to find faults in combinational circuits. The authors framed a new technique comprising of three phases. The first phase identifies...
The aim of the presented work is to improve the quality of testing of SoC digital cores surrounded with test wrappers. The paper presents a new effective delay fault test generation method for the transition faults based on the skewed-load test. The generated delay fault test can be applied to a SoC core through a test wrapper architecture with only a simple boundary scan chain. This eliminates the...
A technique is described for the automatic insertion of fault models into VHDL gate models, using a specific algorithm to calculate fault coverage. This procedure does not require any modification to the structural description of a circuit using these models. Additional optimized algorithms are added to illustrate better calculation of fault coverage of a VHDL based combinational logic circuit.
This paper discusses a test generation method to derive high quality transition tests for combinational circuits. It is known that, for a transition fault, a test set which propagates the errors (late transitions) to all the primary outputs reachable from the fault site can enhance the detectability of unmodeled defects. In this paper, to generate a minimum test set that meets the above property,...
The objective of using logic BIST for online and periodic testing is to identify defects, like opens, resulting from the wear and tear of the circuit. We have shown that existing test sets have a low coverage for open defects located in scan flip-flops, even though such defects may affect functional operation. Existing Logic BIST structures suffer from the same limitations. A novel Logic BIST architecture...
Transient faults have become increasingly observable in combinational logic. This is due to the weakening of some inherent protective mechanisms that logic traditionally holds against such flawed spurious events. One of the aforementioned mechanisms relates to the propagation of transient faults along sensitizable paths. Existing literature that relies on logic simulation under estimates the number...
In this paper, we investigate optimum radiation hardened by design (RHBD) for use against single-event transients (SET) using low-pass filters (LPF) including RHBD techniques against single-event upsets (SEU) for sequential logic in 45 -nm technology in a terrestrial environment. Three types of LPF were investigated regarding their SET pulse immunities, area penalties, and performance penalties. We...
In this paper, we present a novel technique for online testing of feedback bridging faults in the interconnects of the cluster based FPGA. The detection circuit will be implemented using BISTER configuration. We have configured the Block Under Test (BUT) with a pseudo-delay independent asynchronous element. Since we have exploited the concept of asynchronous element known as Muller-C element in order...
Quantum cellular automata (QCA) circuits, the new generation nanotechnology with wide attention in recent years. In this we are proposing a framework based on QCA for finding out the stuck-at fault of a circuit. The existing technologies and methods are not guaranteed to detect the stuck-at faults. This work is motivated by the fact that the stuck-at fault test set of a circuit is not guaranteed to...
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