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A low voltage current sensing circuit is presented in this paper. The proposed current sensing circuit performs continuous-tracking with high accuracy over 98% is achieved. The current sensing circuit is implemented with a standard 0.18μm CMOS process at 1.5V supply voltage. The power efficiency obtains 89% over the maximum load current of 540mA. Wide operation frequency range from 400kHz to 25MHz...
Power efficiency is a very important issue for portable electronic devices since it determines the battery life. The backlight module usually accounts for the major part of power dissipation in a portable device. Thus, to extend the operation time of a portable device, a high efficiency backlight module should be employed. White light-emitting diodes (WLEDs) have replaced cold cathode fluorescent...
In this paper, a new circuit topology to realize a stacked self-oscillating LNA-Mixer is proposed. The basic idea has been to recognize that in a high-performance down-conversion mixer its RF input-stage gain, linearity, and noise tradeoff is often improved by feeding it with a bypass current source. This current source could be isolated with an inductor so as to allow free implementation of the oscillator...
This paper presents a new compact and comprehensive design methodology for RF CMOS source degenerated cascode dual functionality low-noise amplifier (LNA) and power amplifier (PA) for the IEEE 802.15.4 standard (commercially known as ZigBee). The proposed design methodology is based on simultaneous graphical visualization of the relationship between all relevant performance parameters and the corresponding...
This paper presents a low-power down-conversion mixer for 3.1~4.8 GHz MB-OFDM UWB applications. The proposed mixer is based on folded double-balanced Gilbert cell and employs following techniques: two cross-coupling capacitors at the transconductance stage enhance conversion gain and reduce input noise; two choke inductors reduce flicker noise from the switch quad; tuning capacitors and resistors...
An ultra-low-power LC quadrature VCO (QVCO) is presented. It is designed in a single-poly seven-metal 65 nm CMOS process. To minimize power dissipation an inductor with a high LQ product of 188 nH at 2.4 GHz, and a self-resonant frequency (fo) of 3.8 GHz, was designed. According to SpectreRF simulations the power dissipation is below 250 ??W at a 0.6V supply. At this supply the simulated tuning range...
This paper presents an electromagnetic simulation-based modelling solution for active and passive devices which targets 60 GHz front-end integrated circuits. An EM model, using existing transistor compact models as core, is developed to account for the parasitic elements due to wiring stacks. A spiral inductor lumped model, based on EM simulation S-parameter data is also derived. The models are process...
A fully integrated voltage-controlled oscillator (VCO) in SMIC 0.18-μm 1P6M CMOS technology is presented in this paper. The linear tuning range of VCO is from 2.36GHz to 2.52 GHz. The post simulation results show that the phase noise of the proposed VCO is -118.4 dBc/Hz at 1 MHz offset from the carrier at 2.44 GHz, it meets the requirements for Bluetooth application standard, and the current dissipation...
This paper presents a 60 GHz voltage controlled oscillator implemented in conventional 65 nm CMOS technology. This VCO employs an alternative tuning system based on the Miller capacitance instead of conventional varactors. The presented VCO has a tuning range of 10.5 % and operates in the frequency range of 59.5 GHz to 66.1 GHz. It has an output power of -13 dBm and a phase noise of 80 dBc to -85...
High Performance on-chip inductor is a key enabling element of monolithic RF circuits and radio frequency (RF) system-on-chip. Generally, on chip inductor are planar devices but 3D symmetrical spiral interleaved inductor (3DSII) has been proposed [1] to lower the amount of area consumed by inductor. This paper presents a novel 3D group-cross symmetrical spiral interleaved inductor (3DGCSII), which...
In this paper, influences on CMOS voltage controlled oscillator (VCO) caused by dummy metal fills are investigated. Two fully integrated VCOs are fabricated, tested and verified in 0.18-mum 1P6M bulk CMOS technology. The area-consuming inductors and capacitors of the VCOs are implemented by multilayer complementary-conducting- strip transmission lines (CCS TLs) and metal-oxcide-metal (MOM) capacitors,...
This paper presents a DC-30 GHz single-pole-four-throw (SP4T) CMOS switch using 0.13 mum CMOS process. The CMOS transistor layout is done to minimize the substrate network resistance. The on-chip matching inductors and routing are designed for a very small die area (250times180 mum2), and modeled using full-wave EM simulations. The SP4T CMOS switch result in an insertion loss of 1.8 dB and 2.7 dB...
This paper presents high Q and high current on-chip inductors manufactured in an innovative Radio Frequency (RF) Back End Of Line (BEOL), made of two 3 mum thick top copper levels, integrated in an Advanced Low Power 65 nm RF CMOS technology. Achieved inductors using this optimized RF BEOL are firstly reported, compared with those using one single thick copper level BEOL, and benchmarked with current...
This paper, presents a precise noise figure formula for inductive degeneration CMOS LNAs. Also a fully integrated CMOS LNA with on-chip spiral inductors in 0.18 ??m CMOS technology for 5.5-GHz unlicensed national information infrastructure (U-NII), 802.11a and IEEE 802.11n wireless LAN receivers is presented in this paper. Using a cascode current reuse structure with inter-stage inductors we achieved...
This paper describes theoretical as well as practical aspects in designing low phase noise LC CMOS oscillators. It starts with an overview of the different oscillator performance parameters found in a typical oscillator specification sheet. It also describes the LC-tank oscillation phenomena by analyzing a simplified LC oscillator circuit. Oscillator phase noise analysis is then introduced as a logical...
A 24 GHz 130-nm CMOS quadrature voltage controlled oscillator using 4-bit switched frequency tuning is presented. It consists of two differential oscillators coupled to oscillate in quadrature through transistors and mutual inductance between the source nodes. The frequency tuning is accomplished by 4 bits controlling an array of MOS varactors in each resonance tank, combined with a small continuously...
This paper presents a fully integrated single-ended low noise amplifier (LNA) for GSM (GSM850 and GSM900) and UMTS (UMTS Band V and VI). The design and implementation is based on inductively-degenerated common-source (IDCS) using 0.18 μm CMOS technology with on-chip inductors at the input circuit for input matching and extra on-chip RL components at load tank for output matching. Post layout simulation...
Enhanced analytical equations are derived to predict the inductance and series resistance of a common active inductor configuration. The equations, based on MOSFET small-signal parameters, are used to predict the inductance and series resistance of an active inductor implemented in a 0.18 ??m CMOS process. The inductor's characteristics are presented, demonstrating analytical equation accuracy and...
This paper presents the design of a 900 MHz LC oscillator implemented in 0.18 mum RF CMOS technology. Employing an on-chip PN varactor together with an on-chip spiral inductor, this voltage-controlled oscillator (VCO) achieves a simulated phase noise of - 100.9 dBc/Hz at a 100 kHz offset. The output frequency of the VCO can be tuned from 785 MHz to 955.6 MHz which correspond to 170.6 MHz tuning range,...
A complete strategy to manage dummy fills inside and underneath a large spectrum of integrated RF inductors realized in a 0.13 mum CMOS technology using a Damascene Copper Back End of Line (BEOL) is presented here. The main motivation of this paper is first to evaluate through a Design Of Experiment (DOE) modeling, the impact on RF inductor performances of dummy fills inserted inside or underneath...
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