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In order to reduce the pressure of data storage and transmission on satellite, researchers implemented a method of object region data extraction from remote sensing image in orbit. This method stores and downloads pixels of interesting region through interesting region labeling. But encoding data volume (EDV), hardware scale and real-time property (RTP) are difficult to be balanced. To solve this...
This paper presents FPGA implementations of add/subtract algorithms for 10's complement BCD numbers. Carry-chain type circuits have been designed on 6-input LUT's Xilinx Virtex-5 FPGA technologies. Some new concepts are reviewed to compute the P and G functions for carry-chain optimization purposes. Designs are presented with the corresponding time performances and area consumption figures. Results...
Protecting an implementation against side channel analysis for reverse engineering (SCARE) attacks is a great challenge and we address this challenge by presenting a first proof of concept. White-box cryptography has been developed to protect programs against an adversary who has full access to their software implementation. It has also been suggested as a countermeasure against side channel attacks...
Memory is one of the most restricted resources in embedded system. Code compression techniques address this issue by reducing the code size of programs. Huffman coding is the most common used coding method. But during the process of generating symbols from instruction, an experience-based partition way is usually used, which may cause information redundancy. This paper presents an optimal-partition...
CRC (cyclic redundanncy check) block was developed on FPGA (field programmable gate array) in order to meet the needs for simple, low-power and low-cost wireless communication such as Zigbee. Zigbee operates primarily in the 2.4 GHz band, which makes the technology easily applicable and worldwide available. This paper gives a short overview of CRC block in the digital transmitter based on Zigbee standard...
Generally, the traditional SDRAM controllers use an arbitral form to deal with the variable accessing requirement. But the design of the arbitral form is very complex. To avoid the complexity, this article introduces a time-partition form SDRAM controller based on multi-DAB project, and compares the arbitral form controller and the time-partition form. At last, the paper analyzes the new form of SDRAM...
This paper proposes an area efficient signal processing architecture to perform IDDT test calibration through vector multiplication. The design follows the field programmable array organization, and capitalizes on the unique behavior of binary encoded signals to implement compact multiply elements. Vectors with 8 bit values were multiplied at a rate of 300 kHz, independently of vector size.
A new design of HDB3 encoder / decoder based on FPGA is proposed to deal with the high complexity and long output delay of the encoder and no error correction function of the decoder which have been implemented so far. The encoder has the function of converting a NRZ code sequence to a HDB3 sequence and the decoder, vice versa. Meanwhile the decoder can correct the errors in the received HDB3 sequence...
In this paper, we propose a new parallel-pipeline approach to design small-area low complexity convolutional encoders, suitable for high data throughput communication applications. This approach can apply both to the OTM (one to many) and the MTO (many to one) encoder schemes. Here, we will discuss the problem of designing a low cost parallel-pipeline encoder for the MTO case. The new architecture...
Lossless compression is widely used to improve both memory requirement and communication bandwidth in embedded systems. Dictionary based compression techniques are very popular because of their good compression efficiency and fast decompression mechanism. Bitmask based compression improves the effectiveness of the dictionary based approaches by recording minor differences using bitmasks. This paper...
In this paper a methodology of symbolic RTL synthesis, for circuits implemented in FPGA devices, is presented. First, symbolic functions are separated from binary and arithmetic ones. Next, the multi-valued logic network is optimized using our methods of symbolic functional decomposition, designed for functions with multi-valued inputs and multi-valued outputs. Finally, the whole circuit is implemented...
Packet classification has been critical data path function for supporting quality of service (QoS), resource reservation protocol (RSVP) and broad range of multimedia services. Hardware based solution is necessary to keep up with high-speed rate up to OC192 processing. However, the range match in multi-fields classification is still one of the bottleneck problems. In this paper, a novel structure...
A method to efficiently transmit FEC-coded frames in PCS for Ethernet PON is proposed. Comparing with IEEE 802.3ah Clause 65.2.3, the proposed architecture requires only one 8b/10b encoder and is IEEE 802.3ah-compliant. This method speeds up the circuit and reduces the gate counts. In StratixII EP2S180 FPGA, the proposed method, comparing with the standard, saves 40.7% ALUs and increases 18% speed...
Decimal arithmetic is important in several commercial applications including financial analysis, banking, tax calculation, currency conversion, insurance, and accounting. This paper presents a fully parallel Decimal64 floating point (FP) multiplier compliant to IEEE Std 754-2008 for floating point arithmetic. The proposed multiplier possesses novel methods to target low latency. The proposed design...
This paper describes the algorithm and design tradeoffs for multiple hardware implementations of parallel high-radix scalable Montgomery multipliers. Hardware implementations of Montgomery multipliers require choosing a radix, shift direction, and whether to use Booth encoding. Presented are processing element designs exploring combinations of radices 2, 4, and 8, right vs. left shifting, and Booth...
Based on the study of IEEE-1355 communication bus protocol in rugged environment, this paper puts forward a scheme of wormhole routing in network layer. Also a prototype of this wormhole router based on FPGA in rugged environment is designed and implemented. Experiment result shows that this solution can meet the demand of IEEE-1355 communication bus.
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