The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
Median filters commonly used in image processing applications for the removal of impulse noise. Over the years so many median filters such as are separable median filters, recursive median filters, weighted median filters, max-median filters and multistage median filters were developed. Sorting networks are of major concern for real time hardware implementation of filters. Sorting is a computationally...
In this paper, new area minimized architecture is proposed for median filters based on modified decomposition algorithm. The modified decomposition replaces the complexity of existing threshold decomposition algorithm such as complex comparators. The proposed algorithm works in two stages, decomposition and recombination. The proposed algorithm removes the need for 0 to 255 threshold gray levels for...
In this work the image is segmented effectively based on texture feature by reducing the noise. For effective image segmentation Expectation-Maximization (EM) algorithm based on Gabor filter is used. The EM algorithm is applied on 2D Ultrasonic image of uterus and tested. The Gabor function has been recognized by its multiresolution properties and the precision of locating the texture features in...
In this paper an optimized architecture of bit plane coder for Embedded Block Coding with Optimal Truncation (EBCOT) algorithm targeting its FPGA implementation is proposed. Although several speed up techniques exist, we present architecture whose performance is improved based on detailed analysis of data path used to obtain context windows. Multiplexer based coding style is adapted to utilize the...
The power analysis attacks have become a major threat to the cryptographic chips, especially in financial fields. Many countermeasures against these attacks have been proposed, and most of these countermeasures are focused on the microcontroller-based implementations. In this paper, a novel VLSI design of 3DES circuit is achieved for IC bankcard, and "random insertion of dummy cycles" is...
The limitation of speed of modern computers in performing the arithmetic operations such as addition, subtraction and multiplication suffer from carry propagation delay. Carry free arithmetic operations can be achieved using a higher radix number system such as Quaternary Signed Digit (QSD). We proposed fast adders based on Quaternary signed digit number system. In QSD, each digit can be represented...
In this paper, VLSI architectures and FPGA implementation for edge-preserving filter are presented. We proposed two architectures for edge preserving filter: full parallel pipelined and structure-shared architectures. The edge-preserving filter uses adaptive coefficient mask based on the intensity distance in filter blocks. Compared with the bilateral filter, the proposed edge-preserving filter provides...
H.264/AVC has considerably complex derivation process of motion data in comparison with that of previous video standards. It mainly results from advanced motion vector prediction process to cope with various macroblock partitions and spatial/temporal direct modes. This paper addresses the efficient hardware design of the motion vector processor of full-compliant H.264/AVC High Profile (HP) decoder...
The application of independent component analysis (ICA) algorithm can achieve a real time blind signal separation (BSS) if it is physically implemented using hardware devices. However, due principally to both of the limited size and of the microelectronics technology of the used hardware devices, many practical problem can be encountered to reach the real time processing since the application of the...
This paper presents a hardware implementation in a FPGA circuit of an efficient encryption algorithm based on hybrid additive programmable cellular automata (HAPCA). We present a novel approach for a high-speed encryption system prototyped using a single FPGA. The approach is based upon a one-dimensional HAPCA architecture. A regular, modular, and cascadable hardware implementation of the cellular...
Due to aggressive technology scaling VLSI circuits have become more susceptible to transient errors. The associated reduction in supply voltages has decreased noise margins, causing system reliability to be reduced increasingly at a time when electronic systems are being used in ldquosafety criticalrdquo applications. Clock distribution issues as well as the demands for low power circuits have exposed...
This paper presents a VLSI hardware implementation of a manchester and differential manchester coder / decoder systems. VHDL (VHSIC hardware description language) has been used for describing the hardware of the circuit, and field programmable gate arrays (FPGAs) has been used for the hardware implementation task. The data rate can be easily reconfigured, since the target technology (FPGA) can be...
In this paper, we propose a VLSI architecture and an FPGA implementation of a hybrid message-embedding (HME) self-synchronizing stream cipher encryption based on a switched linear congruent pseudo-random generator. This encryption, which is based on a chaotic scheme, is particularly attractive since it provides the same security as any conventional self-synchronizing stream cipher requiring only additions,...
One of the main drawbacks of vector quantization (VQ) image compression is computation complexity in encoding process. A novel algorithm based on cross mean order codebook, is presented to reduce codeword search computation, and its VLSI implementation architecture of VQ encoder is proposed. The FPGA implementation results show that the proposed architecture will reduce three-quarter coding computation...
Low-density parity-check (LDPC) code is one kind of prominent error correcting codes (ECC) being considered in next generation industry standards. This paper presents an FPGA implementation of array code based low-density parity-check code decoder. The advantages of the proposed architecture as compared to the fully parallel or partially parallel architecture are: less memory requirement, avoidance...
In this paper, field-programmable gate array (FPGA) implementations of FIR Nyquist filters are presented. Array processor realizations for FIR Nyquist filter are considered and analyzed, namely the direct, transposed, hybrid, and folded forms. Design examples are considered for low-delay and linear-phase FIR Nyquist filters. The filters are then realized as a combination of the appropriate structures...
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.