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Filtering data in real-time requires dedicated hardware to meet demanding time requirements. If the statistics of the signal are not known, then adaptive filtering algorithms can be implemented to estimate the signals statistics iteratively. This paper aims to combine efficient filter structures with optimized code to create a system-on-chip (SOC) solution for various adaptive filtering problems specially...
We report a two-dimensional (2D) pixel block scanning architecture for image segmentation by segment growing. This architecture can optimize processing speed, power consumption, and circuit area by modifying size and shape of the pixel block. Real-time processing can be maintained by using additional the two important techniques of (i) boundary-scan of the grown segment only, (ii) continued block-internal...
Chaotic encryption schemes are believed to provide a greater level of security than conventional ciphers. In this paper, a chaotic stream cipher is first constructed and then its hardware implementation details using FPGA technology are provided. Logistic map is the simplest chaotic system and has a high potential to be used to design a stream cipher for real-time embedded systems. The cipher uses...
We propose a high-speed mixed integer quadratic programming (MIQP) solver on an FPGA. The MIQP solver can be applied to various optimizing applications including real-time robot control. In order to rapidly solve the MIQP problem, we implement reusing a first solution (first point), pipeline architecture, and multi-core architecture on the single FPGA. By making use of them, we confirmed that 79.5%...
Real-time wireless channel simulators are necessary for radio prototyping. Doppler filter is one of the basic building blocks in correlation-based channel simulators. Enormous computational complexity of channel models for new wireless standards like MIMOs prohibit their software realizations (which have traditionally been the case). In first part of this work, we dimension and compare two alternative...
Power consumption has become a limiting factor in next-generation routers. IP forwarding engines dominate the overall power dissipation in a router. Although SRAM-based pipeline architectures have recently been developed as a promising alternative to power-hungry TCAM-based solutions for high-throughput IP forwarding, it remains a challenge to achieve low power. This paper proposes several novel architecture-specific...
This paper presents a direct method of reducing convolution processing time using hardware computing and implementations of discrete linear convolution of two finite length sequences (NXN). This implementation method is realized by simplifying the convolution building blocks. The purpose of this research is to prove the feasibility of an application specific integrated circuit (ASIC) that performs...
Satellites are extensively used by public and private sectors to support a variety of services. Considering the cost and the strategic importance of these spacecrafts, it is fundamental to utilize strong cryptographic primitives to assure their security. However, it is of utmost importance to consider fault tolerance in their designs due to the harsh environment found in space, while keeping low area...
Digital pulse-width modulator (DPWM) is known as the critical module in digital controller application for high-frequency switching mode power supply (SMPS). This paper presents a new Hybrid DPWM architecture operating at high frequency with high resolution. The proposed DPWM takes advantage of the phase-shift function of Digital Clock Manager (DCM) in FPGA, and combines a counter-comparator with...
Wireless sensor network (WSN) applications demand ultra low power devices. Digital Ultra Wideband (UWB) transceiver can be used as the communication module in a WSN due it its potential for location tracking, ranging and low data rate communication. Current digital UWB receiver architecture incorporates heavy parallelism, which significantly increases power consumption, especially during the acquisition...
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