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A new coding concept called credit-based variable-to-variable length (cbv2v) coding is proposed in this paper. A binary cbv2v code is constructed, and analysis of its performance shows that cbv2v coding can achieve much better trade-off among the coding delay, redundancy, and space complexity than does variable-to-variable length (v2v) coding. Specifically, let L be the total number of source words...
Many digital systems benefit implicitly or explicitly from redundant representations to improve their performance. In this work we present a Limited Selective Redundancy Injection (LSRI) method to improve arithmetic unit performance. Our results show that LSRI with Conventional Input Redundant Output (CI-RO) adder improves Ripple Carry Adder (RCA) latency and Power-Delay-Area-Product (PDAP) by about...
Moduli of the form 2n plusmn 1, which greatly simplify certain arithmetic operations in residue number systems (RNS), have been of longstanding interest. A steady stream of designs for modulo (2n plusmn 1) adders has rendered the latency of such adders quite competitive with ordinary adders. The next logical step is to approach the problem in a unified and systematic manner that does not require each...
Present and future semiconductor technologies are characterized by increasing parameters variations as well as an increasing susceptibility to external disturbances. Transient errors during system operation are no longer restricted to memories but also affect random logic, and a robust design becomes mandatory to ensure a reliable system operation. Self-checking circuits rely on redundancy to detect...
In many DSP applications (image and voice processing, baseband symbol decoding in high quality communication channels) several dBs of SNR loss can be tolerated without noticeable impact on system level performance. For power optimization in such applications, voltage overscaling can be used to operate the arithmetic circuitry slower than the critical circuit path delay while incurring tolerable SNR...
Networks on chips (NoCs) provide a mechanism for handling complex communications in the next generation of integrated circuits. At the same time, lower yield in nano-technology, makes self repair communication channels a necessity in design of digital systems. This paper proposes a reliable NoC architecture based on specific application mapped onto an NoC. This architecture is capable of recovering...
Soft errors induced by cosmic radiation have become an urgent issue for ultra-deep-sub-micron (UDSM) technologies. In this paper, we propose a new radiation hardened by design latch (RHBDL). RHBDL can improve robustness by masking the soft errors induced by SEU and SET. We evaluate the propagation delay, power dissipation and power delay product of RHBDL using SPICE simulations. Compared with existing...
Transient faults have become increasingly observable in combinational logic. This is due to the weakening of some inherent protective mechanisms that logic traditionally holds against such flawed spurious events. One of the aforementioned mechanisms relates to the propagation of transient faults along sensitizable paths. Existing literature that relies on logic simulation under estimates the number...
Base on multi-resolution characteristic of wavelet transformation, a dynamic reconstruction method of image pyramids for remote sensing imagery is proposed in this paper. The method can solve the data redundant problems caused by traditional reconstruction methods, for which the correlation characteristic of the data between different pyramid layers is not used. It can effectively reduce the amount...
A principal factor in sensor network design is energy efficiency. In this work, we propose to extend the lifetime of sensor networks using appropriate choice of sensor node distribution. The key idea of our scheme is to deploy more nodes in areas of extensive energy usage. Using this scheme of sensor node distribution, we use probabilistic angular routing to route data packets from the sensor nodes...
For effective application of on-line arithmetic to practical numerical problems, floating-point algorithms for on-line addition/subtraction and multiplication have been implemented by introducing the notion of quasi-normalization. Those proposed are normalized fixed-precision FLPOL (floating-point on-line) algorithms.
This paper deals with hazards on outputs of combinational circuits without feedback for multiple input changes. A procedure is given to decompose a Boolean function into a feedback free circuit. The procedure either gives a logic hazard-free circuit or shows that the Boolean function cannot be broken down into a feedback free circuit which is free of logic hazards for multiple input changes.
This paper deals with hazards on out-puts of combinational switching circuits for multiple input changes. Certain types of function hazards are defined and are shown to be impossible to eliminate with any logic realization. Also, an interrelation between static and dynamic function hazards is established. Hazards due to delays in the logic are defined and a method of elimination is given for both...
This report describes the techniques used to obtain two three-variable universal logic blocks from NAND circuits. The emphasis for one of these ULB's is on minimizing NAND blocks; for the other ULB, it is on minimizing input pins. The techniques used for the three variable ULB realization are extended to handle realization of a four-variable ULB. Possible compromises to be made in the ULB approach...
The inherent problems of data transmission in a strictly feedforward line have been discussed in the literature. In such a line, where the stored data are indexed forward by control pulses moving in a direction away from the data source, if time variations exist in the delays of successive stages then there is always a nonzero probability that two successive control pulses will eventually appear at...
This paper summarizes some rather extensive research on the problem of constructing logic nets out of elements whose timing causes trouble either in their slowness or in their lack of precision. The problem is made precise by setting up a theory of logic nets that is abstract but realistic. Its abstractness consists in its lack of similarity to any particular hardware, and in its strictly mathematical...
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