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The authors carried out three experiments exploring the influence of language similarity on language selection mechanisms. In Experiment 1, The participants were asked to perform the task of language-switching between their two dissimilar but highly proficient languages (Tibetan-Mandarin) ,in which they had to name the pictures quickly and accurately by using the cued language in the picture-word...
This paper investigates the performance of 3-Z-Network boost converter for a standalone Photovoltaic (PV) power generation system. This proposed converter integrates a single-switch with 3-Z-active Network by diodes, capacitors & inductors. The 3-Z structure of the converter improves the energy conversion efficiency with low switching losses and also reduces the shoot through problem. The different...
Multilevel inverters acts as a promising solution for medium voltage, high power applications due to their modularity and reduced voltage stress across the switches. Cascaded H Bridge Multilevel Inverters (CHB-MLI) are being considered as the best choice for grid connected Photovoltaic (PV) systems since they require several sources on the DC side. By means of MLI's, high quality output with less...
This paper presents the basic features of a software system developed to support the teaching of digital logic, as well as the experience of using it in the Digital Logic course taught at the School of Electrical Engineering, University of Belgrade, Serbia. The system has been used for several years, both by students for self-learning and laboratory work, and by teachers to automate the assessment...
In this paper, An approach for generating multi-torus chaotic attractors from a forth-order and fifth-order Jerk system is proposed via constructing a series of staircase functions. The results of generation of multi-torus chaotic attractors is given. Finally, a block circuit diagram is designed for hardware implementation of the multi-torus chaotic attractors.
A novel scheme for reducing the test application time in accumulator-based test-pattern generation is presented. The proposed scheme exhibits extremely low demand for hardware. It is based on a decoder whose inputs are driven by a very slow external tester. Experimental results on ISCAS benchmarks substantiate a test-time reduction of 75%-95% when compared to previously published test-set embedding...
In this paper, we present a systematic method for the designing fault tolerant reversible arithmetic circuits for finite field or Galois fields of the form GF(2m). To tackle the problem of errors in computation, we propose error detection and correction using multiple parity prediction technique based on low density parity check (LDPC) code. For error detection and correction, we need additional garbage...
In this paper a BISR architecture for embedded memories is presented. The proposed scheme utilises a multiple bank cache-like memory for repairs. Statistical analysis is used for minimisation of the total resources required to achieve a very high fault coverage. Simulation results show that the proposed BISR scheme is characterised by high efficiency and low area overhead, even for high defect densities...
While the CMOS analog circuits can be designed with the minimum-gate-length of the fabrication process in the alpha-power law MOSFET model, the length of a MOSFET gate has been chosen to be a larger scale than the minimum-gate-length in the conventional Shockleypsilas square model. In this paper, we describe a 6-b 100 MSPS CMOS current steering digital-to-analog converter (DAC) with the alpha-power...
The next generation of wireless communication is a ubiquitous radio system concept, providing wireless access from short-range to wide-area, with one single reconfigurable and adaptive system for all envisaged radio environments. This paper presents the design approach of RCO (reconfigurable concurrent oscillator) that simultaneously generates two or more signals of different frequencies that eliminate...
In this paper, the design of a compact planar bandpass filter above a defected ground plane is presented. The filter is designed as a combination of microstrip resonators and exploits the properties of a planar electromagnetic bandgap (EBG) structure patterned unto the ground plane of the printed circuit board material to provide a very wide stopband of up to 5 times the fundamental frequency. The...
Video-streaming can now be offered on third-generation (3G) mobile networks. Most research efforts have focused on video download. This paper presents a detailed study of challenges faced for successfully deploying applications requiring life video upload. Both subjective and objective qualities as well as the effects of mobility are analyzed on real 3G networks. Consequently, video profiles are identified...
In deep submicron era, to prevent larger amount of SRAM from more frequently encountered overheating problems and react accordingly for each possible hotspots, multiple ideal run-time temperature sensors must be closely located and response rapidly to secure system reliability while maintaining core frequency. This paper presented a method to extract run-time temperature information from multiple...
A complexity theory for unbounded fan-in parallelism is developed where the complexity measure is the simultaneous measure (number of processors, parallel time). Two models of unbounded fan-in parallelism are (1) parallel random access machines that allow simultaneous reading from or writing to the same common memory location, and (2) circuits containing AND's, OR's and NOT's with no bound placed...
As remarked in Cook (1980), we do not know any nonlinear lower bound on the circuit size of a language in P or even in NP. The best known lower bound seems to be due to Paul (1975). Instead of trying to prove lower bounds on the circuit-size of a "natural" language, this note raises the question of whether some language in a class is of provably high circuit complexity. We show that for...
A synthesis method for multiple-input change asynchronous sequential machines is proposed. The method is based on the self-synchronization principle. The internal states are realized with edge-sensitive flip-flops which are triggered selectively. The new concept of selective triggering or controlled excitation results in considerable saving in logic and more flexible design. The state assignment is...
This paper describes a new approach to the design of combinational logic using large-scale-integrated (LSI) circuit technology. A simple "prototype" logic function of n binary variables is imbedded within an array of at most (n+1) rows and columns. The cells of this array contain 2-input exclusive-OR gates, and its rows are fed by the input variables and logical "1". Its column...
It is generally recognized that asynchronous operation of logic networks offers specific advantages over synchronous operation controlled by a central clock when the network is subject to large or widely varying inter-module propagation delays. In this paper we characterize several previously described techniques for achieving asynchronous operation by a single model. Essential to the model is the...
The notion of asynchronous switching circuit is roughly understood to be a logical circuit, possibly sequential, in which no special synchronizing signals or "clock" are required for proper circuit operation. Many different formulations of this notion appear in the literature, using sequential machine models and networks of logical element models. The following list of references indicates...
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