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Continuous increase in demand for product miniaturization, high package density, high performance and integration of different functional chips has lead to the development of three dimensional packaging technologies. Face-to-face silicon (Si) dies stacking is one of the three dimensional (3D) packaging technologies to form a high density module. In this work, a chip level stacked module was demonstrated...
Amkor's FCMBGA, flip chip package based on transfer molding for high performance device was developed and introduced to industry in 2008[1,2]. During the molding process, bump deformation was not significant, and voids were not observed under flip chip die. Coplanarity with a low coefficient of thermal expansion, CCTETE, substrate construction was similar to a single piece lidded package construction...
Due to the thin structure employed in planar packaging, the high electric field intensity may occur inside the power module, leading to degradation of the dielectric performance. To resolve this issue, the Metal-Posts-Interconnected Parallel Plate Structure (MPIPPS) is used to reduce the high field concentration in the power module. However, the high bonding joint in MPIPPS will cause high thermo-mechanical...
Hybrid vehicle traction applications require compact power modules with high reliability. A major challenge is the lifetime under thermal cycles. While the requirements are moderate with respect to (active) power cycles, there are challenging requests for a high lifetime under (passive) temperature cycles. Base plates and solder interfaces limit the stability for temperature cycles in the classical...
The multiscale method has become a promising tool that could make a significant contribution to the fields of nano-science and technology. The objective of the multiscale method makes it possible to treat ever larger systems.Current study proposes a new model that combines the atomistic and continuum approaches. The continuum model is built on the lattice view and its critical deformation extent is...
The effect of thinning down the chip thickness, will affect the stress pattern in the chip and causes the chip to deform locally when the thickness of the chip is thinner than a certain critical value. Such a local deformation may cause sharp gradient of residual stress around the solder bumps and thus, various failures. This paper shows that by considering the effect of solder bumps on a 50 mum chip,...
Measurement and modeling for the stress on the active area of the die embedded in an organic resin system has been studied. Embedded structure was successfully realized by doing a sequential lamination process using no other materials but conventional build-up materials, used in printed circuit board, in the organic substrate except die. Embedding process consists of lamination process, laser drilling...
This paper presents the study on the effect of bump structure, chip pad structures and die thickness of a large die Cu/low-k chip for improving assembly performance on organic buildup substrate. After assembly with the initial interconnection design, metal cracks at RDL were found for the conventional SnAg bump and Cu post samples. In order to improve the bump structure design a thermo-mechanical...
In engineering applications, piezoelectric materials are usually bonded to elastic substrates to form so-called smart materials and structures. Such materials and structures can respond to external electromechanical environments. This article studies a piezoelectric layer bonded to an elastic substrate subjected to static electromechanical loads, both of which are of finite length. A system of differential...
The influences of statically deformed state including both the elastic and plastic deformations induced by applied uniaxial stresses on the Love waves in layered rocks are investigated on the basis of the acoustoelastic theory for elastic-plastic materials. The phase velocity equations of the Love waves are obtained by direct boundary conditions. The acoustoelastic effects of elastic and elastic-plastic...
This paper presents reliability study of stacked via technology for substrates. It is concluded that to approach product design miniature and cost reduction, stacked via design is key tendency. A reliable stacked via formation need combine with design, material set selection, and process control of via connectivity. The reliability test application of process SQC should be able for process optimization...
Miniaturisation of electronic devices and the RoHS directive have made the use of solder joints challenging. Thus, new methods for attachment of chips have been developed, such as adhesive attachments. Moisture is the principal cause for failures in these attachments. The effects of moisture to non-conductive adhesive attachments were studied by modeling with finite element method and by environmental...
Assembly processes used to bond components to printed circuit boards can have a significant impact on these boards and the final packaged component. Traditional approaches to bonding components to printed circuit boards results in heat being applied across the whole board assembly. This can lead to board warpage and possibly high residual stresses. Another approach discussed in this paper is to use...
A numerical modelling method for the analysis of solder joint damage and crack propagation has been described in this paper. The method is based on the disturbed state concept. Under cyclic thermal-mechanical loading conditions, the level of damage that occurs in solder joints is assumed to be a simple monotonic scalar function of the accumulated equivalent plastic strain. The increase of damage leads...
With the demanding of market, the electronic portable products can be characterized by increasing signal frequencies and higher density of functions. The electronic products are expected to be produced smaller and smaller. There is one way to meet the requirement, which is a three- dimensional integration of components. A new concept of a packaging structure is proposed based on an embedded chip structure...
Polarities of plasma charging damage in n- and p-channel MOSFETs with Hf-based high-k gate stack (HfAlOx/SiO2) were studied for two different plasma sources (Ar-and Cl-based gas mixtures), and found to depend on plasma conditions, in contrast to those with conventional SiO2. For Ar-plasma, which was confirmed to induce a larger charging damage, both n- and p-ch MOSFETs with high-k gate stacks suffer...
Continuous scaling, necessary for enhanced performance and cost reduction, has pushed existing CMOS materials much closer to their intrinsic reliability limits, forcing reliability engineers to get a better understanding of circuit failure. This requires that designers will have to be very careful with phenomena such as high current densities or voltage overshoots. In addition to the reliability issues,...
3D contactless technology based on capacitive coupling represents a promising solution for high-speed and low power signaling in vertically integrated chips. AC coupled interconnects do not suffer from mechanical stress, and the parasitic load is much reduced when compared to standard DC solutions, such as wire bonding and micro bumps. Communication system based on wireless interconnection scheme...
Plasma-exposed Si surface related to Si recess in source/drain region was investigated in detail for various superposed bias configurations with frequencies of 13.56 MHz and 400 kHz. Two different bias powers were utilized by an inductively coupled plasma reactor (ICP). The surface layer (SL) and the interfacial layer between the SL and Si substrate (IL) were analyzed by spectroscopic ellipsometry...
This paper considers mechanical stress and strain in a piezoresistive cantilever sensor under surface stress loading, which is the loading condition that occurs in biochemical sensing applications. Finite element simulations examine the piezoresistor sensitivity due to changes in cantilever length, width, and thickness, and piezoresistor size, location, and depth. A few unexpected results are found...
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