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Reconfigurable hardware is now used in high performance computers, introducing the high performance reconfigurable computing. Dynamic hardware allows processors to devolve intensive computations to dedicated hardware circuitry optimized for that purpose. Our aim is to make larger use of hardware capabilities by pooling the hardware and software computations resources in a unified design in order to...
In this paper we examine the idea of implementing communicating sequential processes (CSP) constructs on a Java embedded chip multiprocessor (CMP). The approach is intended to reduce the memory bandwidth pressure on the shared memory, by employing a dedicated network-on-chip (NoC). The presented solution is scalable and also specific for our limited resources and real-time predictability requirements...
This paper presents a significantly improved strategy for accelerating the method calls in the REALJava coprocessor. The hardware assisted virtual machine architecture is described shortly to provide context for the method call acceleration. The strategy is implemented in an FPGA prototype. It allows measurements of real life performance increase, and validates the whole co-processor concept. The...
In this paper we show how a simple dataflow processor can be fully implemented using CλaSH, a high level HDL based on the functional programming language Haskell. The processor was described using Haskell, the CλaSH compiler was then used to translate the design into a fully synthesisable VHDL code. The VHDL code was synthesised with 90 nm TSMC libraries and placed and routed. Simulation of the final...
This paper describes an FPGA-based system capable of computing the distance of objects in a scene to two stereo cameras, and use that information to isolate objects in the foreground. For this purpose, four disparity maps are generated in real time, according to different similarity metrics and sweep directions, and then merged into a single foreground-versus-background bitmap. Our main contribution...
The scale invariant feature transform (SIFT) is a very efficient algorithm to extract and describe distinctive invariant features from images, and usually applied for many image applications such as object recognition, robotic mapping, and navigation. In the SIFT computation, the complexity of the feature description is quite high. Hence, it is desirable to have an efficient VLSI architecture to compute...
ADL is composed of architecture behavioral description and architecture structural description from two design views. According to Dajski's Y-Chart, ASIP description based on multi-level ADL proposed in the paper could meet the embedded systems design requirements to fill up the gap that exists between the specification level and the implementation level.
With the rapid development of digital TV and deployment of set-top boxes, standardizing remote controllers for both digital TV and set-top box has become an issue for digital TV operators, set-top box producers and remote controller manufacturers. This paper presented a novel method to solve the incompatibility problem among different digital TV sets, set-top boxes and remote controllers. This novel...
Engine control systems, consisted of ECU hardware, software, sensors, and actuators, are the most significant part of automotive control, and can be considered as mixed-signal systems which interact with engine through sensors and actuators. In this article, we present a component-based modeling and simulation framework for automotive system design. This component framework is compatible with AUTOSAR...
Virtualization has been widely used in cloud computing systems to cut costs, and to provide dynamically scalable resources over the internet. Many ideas have been proposed to increase the security of the virtualized systems. But, a big unspoken assumption of these ideas is that the cloud users have to trust the cloud provider totally and unconditionally. In reality, however, this assumption can't...
Multi-parallel architecture for MD5 (Message-Digest Algorithm 5) implemented on FPGA (Field-Programmable Gate Array) is presented in this paper. To accelerate the speed, a general architecture for Host Computer and FPGAs is proposed. The MD5 implementation is presented. Besides the internal parallelization of MD5 modules, FPGAs can be easily duplicated and connected to Ethernet LAN. The design was...
The application of network computing technology, more and more widely, its security is particularly important to the emergence of trusted computing research for the security of network computing application technology research has provided new opportunities. In this paper, the credibility of Web-based computing environment, the structure of thought and its implementation model.
Small cell base stations (BSs) that form an overlay layer on the existing macrocell network offer tremendous potential in terms of satisfying high data rate traffic requirements and enabling breakthrough services. However; small cell deployments can pose negative energy-efficiency implications if not equipped with advanced power saving mechanisms. In this work, we address this issue and propose algorithms...
This paper addresses the issue of encoding of LDPC codes for certain transmission standards that employ LDPC as coding scheme. It is shown that for these LDPC codes, the encoding can be done simply by reusing decoding resources with negligible overhead. Compared to conventional encoding designs, our approach requires much less resources specified for encoder.
System dependability plays an important role in the realization of computer communication infrastructures and the everyday operations and maintenance of computer networks. Increased redundancy is used as a common practice to improve dependability, however in some cases duplication of a networking equipment is not desirable due to high cost or increased system complexity as a result of handling potentially...
Chip Multicore Processor (CMP) has become the mainstream microprocessor architecture in nowadays industry and academic literature. With the progress of CMP hardware developing and researching, software issues become more and more prominent. Coupled with these developments, many institutes and universities change their curriculums of computer architecture related courses. But the problem is do we really...
This paper would like to design the failsafe architecture to ensure the stability and safety of unmanned ground vehicle (UGV). Because the failure in the unmanned systems can cause a nasty accident. So, first, we limit the discussion to the UGV in the unmanned systems. And then we find out failure for the UGV which consists of the variety of the hardware, and discuss the danger. And we define the...
Image segmentation is an important technique in the area of image processing with wide applications in medicine, remote sensing to mention a few. A lot of research work is in progress in various areas resulting in many computationally efficient algorithms. There are conventional as well as improvised segmentation algorithms depending on the application. The choice of the technique in most cases depends...
High performance computing (HPC) by parallel computing effort faces several challenges. The first challenge is the efficient design and management of the parallel computing resources of the hardware platform. The second challenge is the transformation of the sequential program meant for classic Von Neumann architecture to explicit parallel instruction computing (EPIC) architecture. The third challenge...
With the growing needs for advanced functionalities in modern embedded systems, it is now necessary to integrate multiple processors in the system, preferably on a single chip, to support the required computing complexity. The problem is that such multiprocessor system-on-chip (MPSoC) architecture is very complex and its internal behavior is very difficult to track. An effective tool for profiling...
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