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The NoC Architecture plays crucial role while designing communication systems for System on Chip (SoC). The NoC architecture is improved over conventional bus, shared bus design and cross bar interconnection architecture for on chip networks. In order to improve the Quality of Service, Congestion, Throughput and latency in NoC, Hexagonal node based architecture is proposed in our previous paper[14]...
Field-programmable gate arrays (FPGAs) are used in various systems that use reconfigurable function. Conventional FPGAs have been developed by a transistor-level description for minimizing routing delay. Although FPGAs developed by the register transfer level (RTL) design methodology provide various benefits to the designers of a system-on-a-chip (SoC), they have not been realized. Therefore, the...
Design productivity is a major concern preventing the mainstream adoption of FPGAs. Overlay architectures have emerged as one possible solution to this challenge, offering fast compilation and software-like programmability. However, overlays typically suffer from area and performance overheads due to limited consideration for the underlying FPGA architecture. These overlays have often been of limited...
A wave-pipeline is a design technique for achieving high-speed and low-power operations also in field-programmable gate arrays (FPGAs). It realizes pipeline operations by adjusting delay times. Implementation of fine-tuning of wave-pipelines is possible to further increase the throughput. However, in the FPGA, it is not able to be executed by the restriction on the structure. This paper proposes a...
Rapid improvements in integrated circuit technology over the past few decades enable increasingly large and complex Field Programmable Systems-on-Chip (FPSoC). Due to the large number of components used, the traditional bus-based interconnect scheme becomes cumbersome and restrictive. Hence, the Network-on-Chip (NoC) interconnect paradigm becomes appealing due to its many advantages such as scalability...
Due to the ever increased energy consumption, large research effort has devoted to the energy efficiency area. In this paper, a frequency scalable publish-subscribe filter forwarding node has been proposed and implemented for addressing this challenge. The frequency scaling filter can operate on three different frequencies, which adapts its capacity and power on different network throughput. Our work...
Targeting real-time encryption/decryption of high speed data communication, this paper proposes an FPGA-based high throughput AES design. The critical functions involved in AES are broken into elementary logic operations to gain the deep insight into the performance bottleneck. With respect to FPGA structures, a datapath with two balanced pipeline stages is determined for each of the encryption/decryption...
Both Internet and semiconductor technology have advanced dramatically over the past decade. These advancements have made great impact on the conventional Internet infrastructure where networking equipment is dedicated on a per network basis. Router virtualization allows a single hardware router to serve packets from multiple networks while ensuring the same throughput and Quality of Service (QoS)...
Multiprocessor system-on-chip (MP-SoC) platforms are emerging as an important trend for SoC design. Network on Chips (NoC) become the preferred on-chip communication platform for current and future SoC architectures. In this paper, we present the design of a new on chip network with Quality-of Service (QoS) support. The proposed routers use new dynamic arbitration architecture with a priority-based...
We propose a combined length-infix pipelined search (CLIPS) architecture for high-performance IP lookup on FPGA. By performing binary search in prefix length, CLIPS can find the longest prefix match in (log L-c) phases, where L is the IP address length (32 for IPv4) and c>;0 is a small design constant (c=2 in our prototype design). Each CLIPS phase matches one or more input infixes of the same...
Memory efficiency with compact data structures for Internet Protocol (IP) lookup has recently regained much interest in the research community. In this paper, we revisit the classic trie-based approach for solving the longest prefix matching (LPM) problem used in IP lookup. In particular, we target our solutions for a class of large and sparsely-distributed routing tables, such as those potentially...
A reduced-complexity low density parity check (LDPC) layered decoding architecture is proposed using an offset permutation scheme in the switch networks. This method requires only one shuffle network, rather than the two shuffle networks which are used in conventional designs. In addition, we use a block parallel decoding scheme by suitably mapping between required memory banks and processing units...
Advances in optical networking technology are pushing internet link rates up to 100 Gbps. Such line rates demand a throughput of over 150 million packets per second at core routers. Along with the increase in link speed, the size of the dynamic routing table of these core routers is also increasing at the rate of 25-50 K additional prefixes per year. These dynamic tables require high prefix deletion...
Low-density parity-check (LDPC) codes form an important subclass of error correcting coding techniques, and its implementation has been hot spot of domains such as signal process, magnetic recording or next generation communication for years. This paper proposes a configurable FPGA implementation of Partition-and-Shift LDPC decoder based on Min-Sum algorithm. An MPEG algorithm is introduced to reduce...
Since the recent increase in the popularity of services that require high bandwidth, such as high-quality video and voice traffic, the need for 100-Gbps equipment has become a reality. In particular, next generation routers are needed to support 100-Gbps worst-case IP lookup throughput for large IPv4 and IPv6 routing tables, while keeping the cost and power consumption low. It is challenging for today's...
IP address lookup is one of the most important functionalities in the router design. To meet the requirements in high speed routers consisting of line-cards with 40 Gbps transfer rates, researchers usually take lookup/update speed, storage requirement, and scalability into consideration when designing a high performance forwarding engine. As a result, hardware-based solutions are often used to develop...
Most high-speed Internet Protocol (IP) lookup implementations use tree traversal and pipelining. Due to the available on-chip memory and the number of I/O pins of Field Programmable Gate Arrays (FPGAs), state-of-the-art designs cannot support the current largest routing table(consisting of 257 K prefixes in backbone routers). We propose a novel scalable high-throughput, low-power SRAM-based linear...
The paper presents a performance evaluation of MIC@R router for Networks-on-Chip (NoC) design. Its architecture offers lowest routing latency (1 cycle) and allows supporting several adaptive routing algorithms. The proposed router architecture is implemented in ASIC technology and evaluated in 2D Mesh networks with four routing schemes: Deterministic, Fully Adaptive (FA), Proximity Congestion Awareness...
A new high density, high performance radiation hardened, reconfigurable field programmable gate array (FPGA) is being developed by Achronix Semiconductor and BAE Systems for use in space and other radiation hardened applications. The reconfigurable FPGA fabric architecture utilizes Achronix Semiconductor novel picoPIPE technology and it is being manufactured at BAE Systems using their strategically...
We present Omnipresent Ethernet - by using binary and source routing embedded in Carrier Ethernet advances as a method for providing end-to-end communication in metro networks. A test-bed is built to showcase triple play applications.
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