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There is an increasing availability of high throughput networks which leads to the need of security appliances in these networks. Testing these appliances with regards to performance and effectiveness relies on testing tools that can achieve or even surpass the capabilities of the devices and networks under test. However, current tools are not capable of achieving both the flexibility and performance...
The growing popularity of high performance computing has led to a new focus on bypassing or eliminating traditional I/O operations that are usually the bottlenecks for fast processing of large data volumes. One such solution uses a new network communication protocol called InfiniBand (IB) which supports remote direct memory access without making two copies of data (one in user space and the other...
Benchmark SpecWeb 2009 is usually adopted to measure the performance of server systems. Most of the submitted scores in SPEC official web site are measurements of single node servers. This paper proposes a method of running SpecWeb 2009 on a high-density and low-energy cloud server. The cloud server is a cluster of "big nodes", each of which has 8 computing modules containing 4 Intel Xeon...
Conventional reliability testing of microelectronic power devices requires dedicated test systems. In order to test a statistically meaningful set of devices, only simplified stress pattern generation through a centralized controller is performed due to cost restrictions. Knowledge about device performance and failure time is commonly obtained by periodically removing the device from the test setup...
A key challenge currently limiting the wide spread acceptance of Cu(In,Ga)Se2 (CIGS) thin-film photovoltaic technologies in building integrated photovoltaic (BIPV) systems is the demonstration of product reliability in accelerated testing to support rapid product improvement cycles and new product introduction. To augment multi-year & geographically diverse real world performance a priori, one...
The paper contributes to system level diagnostics by two new diagnostics algorithms for faulty units identification in regular computing systems from testing results. The developed algorithms are based on the symmetric diagnostics model at system level. Effectiveness and complexity of the implemented algorithms were evaluated by experiments over several regular computing architectures (hypercube,...
We elaborate on the theoretical foundation and practical application of the contract-based specification method originally developed in the Integrated Project SPEEDS, for two key use cases in embedded systems design. We demonstrate how formal contract-based component specifications for functional, safety, and real-time aspects of components can be expressed using the pattern-based requirement specification...
Proposed architectural advancements focus on solutions for known deficiencies. Validation of the proposals sometimes is limited to simple scenarios where the deficiency exists. Due to simulation overhead, the validation testing may be limited to small test scripts, and may not include the entire target environment in which the proposed architectures would be eventually applied. A case study is presented...
Due to their reconfigurability and their high density of resources, SRAM-based FPGAs are more and more used in embedded systems. For some applications (Pay-TV,Banking, Telecommunication ...), a high level of security is needed. FPGAs are intrinsically sensitive to ionizing effects, such as light stimulation, and attackers can try to exploit faults injected in the downloaded configuration. Previous...
This paper describes several methodologies based on a pulsed laser beam to reveal the architecture of a high integrated SDRAM, and the different classes of Single Event Effects that can occur due to cosmic radiations. At cell level, laser is used to reveal an important technological parameter: the lithography process. At memory array level, laser is a powerful tool to retrieve cell physical arrangements,...
We present a practical, systematical method for the evaluation of the soft error rate (SER) of microelectronic devices. Existing methodologies, practices and tools are integrated in a common approach while highlighting the need for specific data or tools. The showcased method is particularly adapted for evaluating the SER of very complex microelectronic devices by engineers confronted to increasingly...
Cryptographic devices are recently implemented with different countermeasures against side channel attacks and fault analysis. Moreover, some usual testing techniques, such as scan chains, are not allowed or restricted for security requirements. In this paper, we analyze the impact that error detecting schemes have on the testability of an implementation of the advanced encryption standard, in particular...
Field programmable gate arrays (FPGAs) are getting more and more attractive for military and aerospace applications, among others devices. The usage of non volatile FPGAs, like Flash-based ones, reduces permanent radiation effects but transient faults are still a concern. In this paper we propose a new methodology for effectively measuring the width of radiation-induced transient faults thus allowing...
In many DSP applications (image and voice processing, baseband symbol decoding in high quality communication channels) several dBs of SNR loss can be tolerated without noticeable impact on system level performance. For power optimization in such applications, voltage overscaling can be used to operate the arithmetic circuitry slower than the critical circuit path delay while incurring tolerable SNR...
This document presents a compilation of results from tests performed by iRoC Technologies on SER induced by alpha particles on SRAM memories for technology nodes from 180 nm to 65 nm. The aim of this study is to establish the variation of sensitivity with technology node for SEU and MCU, and to analyze the possible influence of different designs and technological parameters at a given technology node.
The paper addresses the problem of creating a comprehensive fault injection environment, which integrates and improves various simulation and supplementary functions. This is illustrated with experimental results.
Soft errors caused by ionizing radiation have emerged as a major concern for current generation of CMOS technologies and the trend is expected to get worse. Soft error rate (SER) measurement, expressed as number of failures encountered per billion hours of device operation, is time consuming and involves significant test cost. The cost stems from having to connect a device-under-test to a tester for...
This paper presents an architecture to support fast prototyping of augmented reality systems, based on virtual reality. The architecture defines simulation services separated from other aspects of the system. These services support incremental evolution of simulated prototypes into nonsimulated systems. Focus is also placed on user interaction,through the definition of an interaction architecture...
In this paper, we present a novel technique for online testing of feedback bridging faults in the interconnects of the cluster based FPGA. The detection circuit will be implemented using BISTER configuration. We have configured the Block Under Test (BUT) with a pseudo-delay independent asynchronous element. Since we have exploited the concept of asynchronous element known as Muller-C element in order...
Advances in micromachining technology can facilitate the integration of SAW (Surface Acoustic Wave) devices and CMOS circuitry on IC scale substrate for Monolithic fabrication. The optimal design and performance of these filters can be reached by using new Smart materials. The key component in the structure of the SAW device is the piezoelectric materials used which depends mainly on some important...
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