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With the large scale application of integrated circuit in the chaotic encryption, the design of cryptogram program based on the chaotic system becomes a new trend of cryptography. The digital degradation after the chaotic digitization is a key issue to be resolved, while current study pays more attention to digital chaotic period behavior, but the other characteristics of digital chaotic also plays...
A higher level, for the Nios II soft processor realizes the IFF encryption authentication technology is discussed in this paper. Through configuration Secure Hash Algorithm (SHA-1) on the Nios II soft processor within Altera FPGA, and communication with the secure EEPROM, an Identification Friend or Foe is completed. This method can provide secure IP protection and license management solution for...
Multi-parallel architecture for MD5 (Message-Digest Algorithm 5) implemented on FPGA (Field-Programmable Gate Array) is presented in this paper. To accelerate the speed, a general architecture for Host Computer and FPGAs is proposed. The MD5 implementation is presented. Besides the internal parallelization of MD5 modules, FPGAs can be easily duplicated and connected to Ethernet LAN. The design was...
This paper presents an FPGA implementation of Advance Encryption Standard (AES), using Minimal Instruction Set Computer (MISC) with Harvard Architecture. With simple logic components and a minimum set of fundamental instructions, the MISC using Harvard Architecture enables the AES encryption in severely constraint hardware environment, with lesser execution clock cycles. The MISC architecture was...
Embedded systems have become more and more important in our lives. However almost the security protections dedicates in the PC system defense, and there is little effort in the research of the embedded systems security. Embedded systems are in danger. What is more, there are varied kinds of embedded systems platforms, which exacerbate the protection in the embedded systems. This paper is going to...
The MICKEY 128 (Mutual Irregular Clocking KEY stream generator with a 128-bit key) is a stream cipher designed in response to the ECRYPT “Call for Stream Cipher Primitives” in 2005. For many applications, these implementations need to be resistant against side channel attacks, means; it should not be too easy to extract secret information from physical measurements on the device. This paper presents...
Advanced Encryption Standard (AES) and state of art technology FPGAs (Field Programmable Gate Arrays) can be used together to mitigate the potential threats of interception of Satellite data and unauthorized access to the Satellite System. This paper discusses the implementation and verification of AES algorithm on Virtex 4 FPGA and its usage in the protection of Remote Sensing Satellite Data. The...
A new ultra-high frequency radio frequency identification (UHF RFID) reader which baseband module is based on ARM processor and FPGA chip has been designed and implemented to satisfy EPC Class-1 Generation 2 protocol. The reader consists of three parts: baseband signal processing board, radio frequency transceiver and interface board. 90 degree phase-shift microstrip line is used in the radio-frequency...
Multi-cipher and multi-mode cryptosystems are widely used for hardware acceleration in modern security protocols. In a session of communication, these protocols can only use an algorithm along with its operation mode. The switching of cipher algorithms and operation modes can occur between sessions of communication. This paper introduces a multi-cipher cryptosystem (MCC) which enables a cryptosystem...
This paper presents the implementation of a tightly coupled hardware architectural enhancement to the Altera FPGA-based Nios II embedded processor. The goal is to accelerate Advanced Encryption Standard (AES) operations in 128, 192 and 256-bits, for application in a high-performance embedded system implementing symmetric key cryptography. The concept is to augment the embedded processor with a new...
A design comprised of multiple licensed Intellectual Property (IP) blocks presents a significant challenge for protecting the rights of the IP owners. This paper presents the extension of a previously introduced protection mechanism for IP owners' rights to System-on-Chip designs comprised of multiple licensed IP cores and non-licensed user-designed modules.
In this paper, techniques to perform power analysis attacks to snatch confidential data from cryptographic circuits are quantitatively compared. In particular, the popular Differential Power Analysis (DPA) and Correlation Power Analysis (CPA) techniques are compared in terms of their effectiveness, explicitly considering both precharged and static logic styles. The analytical evaluation of the main...
Since its adoption as a new encryption standard by NIST, the Advanced Encryption Standard (AES) has become the default choice for various security services in many applications. On the other hand, a straightforward hardware implementation of the AES may not satisfy the tight constraints of several resource limited devices such as radio frequency identification (RFID) tags and tiny sensor networks...
This paper presents the design of an ultra high speed crypto-processor for next generation IT security. It addresses the next generation IT security requirements: the resistance against all attacks and high speed with low latency. The proposed processor is capable of generating cryptographically secured information at a rate of multi-ten Gbps. The performance of the processor is compared with that...
It has become clear that the current generation of cryptographic hashing algorithms are insufficient to meet future needs. Hash functions are among the most widespread cryptographic primitives, and are currently used in multiple cryptographic schemes and security protocols such as IPSec and SSL. In this paper, a hardware implementation of the newly proposed draft hash standard SHA-512 achieves high...
Since their introduction by Kocher in 1998, power analysis attacks have attracted significant attention within the cryptographic community. While early works in the field mainly threatened the security of smart cards and simple processors, several recent publications have shown the vulnerability of hardware implementations as well. In particular, field programmable gate arrays are attractive options...
One of the key problems facing the computer industry today is ensuring the integrity of end-user applications and data. Researchers in the relatively new field of software protection investigate the development and evaluation of controls that prevent the unauthorized modification or use of system software. While many previously developed protection schemes have provided a strong level of security,...
The "PYRAMIDS" block cipher is a symmetric encryption algorithm of a 64, 128, 256-bit length, that accepts a variable key length of 128, 192, 256 bits. The algorithm is an iterated cipher consisting of repeated applications of a simple round transformation with different operations and different sequence in each round. The algorithm was previously software implemented in C++ code. In this...
The following topics are dealt with: field programmable technology; arithmetic; reconfiguration mechanisms; custom computing; FPGA applications; configurable architectures; security; and reconfigurable applications
In order to provide a capability for secure remote reconfiguration of FPGAs, FPGA bitstream needs to be encrypted and authenticated during its transmission through any public network. Bitstream encryption is already implemented in a few modern FPGA families, such as Xilinx Virtex II. An important feature lacking in the current generation of FPGAs is the ability to cryptographically verify the authenticity...
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