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This paper presents a new low complexity architecture of least-mean-square (LMS) adaptive filter using distributed arithmetic (DA). The DA based LMS adaptive filter requires lookup tables (LUTs) for filtering and weight updating operation whose complexities grow exponential with filter order. In the proposed technique, the complexity of LUT for DA based LMS adaptive filter is reduced by two new serial...
In this paper, we propose an energy-efficient approximate multiplier design approach. Fundamental to this approach is configurable lossy logic compression, coupled with low-cost error mitigation. The logic compression is aimed at reducing the number of product rows using progressive bit significance, and thereby decreasing the number of reduction stages in Wallace-tree accumulation. This accounts...
This paper mainly presents a design of optimized (15, 4) parallel counter. When testing the design with 15 rows of inputs, synthesis report of our design performs better in respect of delay, area and power consumption than other two existing design. This result shows that processes such as partial product reduction in a multiplier or column-addition in a matrix could be more efficient, especially...
In this paper, we proposed a new design of hybrid adder for area-efficient 32-bit floating point multiplier. By combining conventional ripple carry adder (RCA) and Wallace tree adder for adding Generated Partial Products (GPPs), the speed can be improved. Toom-3 multiplication method applied on 24×24 mantissa multiplier with a reduced complexity of (n1.465). Pre-determined Partial Products Generation...
Stochastic turbo decoder is a new scheme for turbo codes. But the long decoding latency and high complexity are two main challenges for fully parallel stochastic turbo decoders. In this paper, we proposed a novel stochastic turbo decoder scheme with two high accuracy stochastic operator modules, including no-scaling stochastic addition and stochastic normalization operator, which can improve the decoding...
In two recent contributions, minimization of number of adders in realization of digital finite impulse response (FIR) filter has been discussed. The proposed method extends the concept of these techniques to further reduce the requirement of adders in FIR filter for different applications. This paper is based on merging of concepts involved in vertical and horizontal common sub-expression elimination...
For multiplierless FIR filter design and implementation, optimization of the product accumulation block (PAB) in transposed direct form structure has been ignored by most of the research. In this work, the power consumption of the PABs of FIR filters is studied theoretically and experimentally. It is shown that the PAB contributes most of the total power consumption in multiplierless FIR filters....
In this paper, the high throughput hardware architecture is designed to calculate the Sum of Absolute Difference (SAD) based on the variable block size of the image. Even though the fixed block size motion estimation is simple with respect to the complexity of the variable block size motion estimation, variable block size estimation technique results in exquisite performance. Motion estimation is...
In previous work, a fully predictable sub-linear runtime heuristic for the multiplication by a constant based on Radix-2r arithmetic using a fixed radix was developed, called RADIX-2r. In this paper, we introduce a new constant multiplication algorithm based also on Radix-2r arithmetic but considering a variable radix. The new version is named RADIX-2r-VAR. Using a variable radix allows to optimize...
We consider an uncoordinated Gaussian multiple access channel with a relatively large number of active users within each block. A low complexity coding scheme is proposed, which is based on a combination of compute-and-forward and coding for a binary adder channel. For a wide regime of parameters of practical interest, the energy-per-bit required by each user in the proposed scheme is significantly...
This paper presents a technique for addition/subtraction in the Logarithmic Number System (LNS) which is based on Floating Point addition/subtraction, specifically on fractional normalization (FN). The proposed technique is analyzed and compared with two other methods for addition/subtraction using 11- and 17-bit word lengths. The results are demonstrated by evaluating complexity and performance of...
Latest developments in satellite communications encompass semi-transparent transponder architectures. Such architectures have potentials i) to operate with enhanced frequency planning flexibility and physical layer specifications of evolving communications standards, and ii) to support dynamic reconfiguration of connectivity plans, especially desirable in packet switching transport modes. In this...
Multiple-valued logic (MVL) has potential advantagesfor energy-efficient design by reducing a circuit complexity. Because of physical device and circuit realization issues, however, there are relatively small number of researches on MVL circuitdesigns. We design a novel ternary multiplier based on a ternaryCMOS (T-CMOS) compact model. To estimate performance andenergy efficiency of our ternary design,...
Video processing performed directly on IoT nodes is one of the most performance as well as energy demanding applications for current IoT technology. In order to support real-time high-definition video, energy-reduction optimizations have to be introduced at all levels of the video processing chain. This paper deals with an efficient implementation of Discrete Cosine Transform (DCT) blocks employed...
Approximate arithmetic has recently emerged as a promising paradigm for many imprecision-tolerant applications. It can offer substantial reductions in circuit complexity, delay and energy consumption by relaxing accuracy requirements. In this paper, we propose a novel energy-efficient approximate multiplier design using a significance-driven logic compression (SDLC) approach. Fundamental to this approach...
Reversible computation became established as a promising concept due to its application in various areas like quantum computation, energy-aware circuits, and further areas. Unfortunately, most functions of interest are non-reversible. Therefore, a process called embedding has to be conducted to transform a non-reversible function into a reversible one — a coNP-hard problem. Existing solutions suffer...
Low-power approximate adders provide basic building blocks for approximate computing hardware that have shown remarkable energy efficiency for error-resilient applications (like image/video processing, computer vision, etc.), especially for battery-driven portable systems. In this paper, we present a novel scalable, fast yet accurate analytical method to evaluate the output error probability of multi-bit...
Systematised classes arithmetic and logical operations and functional operations in different theoretical and numerical basis. Investigated the system characteristics of one-bit half-adder. The proposed the circuit engineering solution of synthesis of half-adder with functional completeness of inputs and outputs and maximum speed 1 mikrotakt based on logic elements AND-NOT, which simplifies their...
The widely using CMOS technology implementing with irreversible logic will hit a scaling limit beyond 2020 and the major limiting factor is increased power dissipation. The irreversible logic is replaced by reversible logic to decrease the power dissipation. The devices implemented with reversible logic gates will have demand for the upcoming future computing technologies as they consumes less power...
In the Modern computers for performing the operationof ALU (Arithmetic Logic Unit) like Addition, Subtraction, different types of adders are using for achieving low delay and fastoutput. QSD numbers are using for giving the carry-free additionso that ALU operations can perform in low delay and speed of themodern computer can increase. In the modern digital system fastadder, Subtraction can perform...
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