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The studies of the low frequency noise in graphene transistors with the number of carbon layers from N=1 (single layer graphene) to N=15 showed that 1/f noise becomes dominated by the volume noise when the thickness exceeds approximately 7 atomic layers. We compare these results with the data on surface and volume noise in carbon nanotubes and Si MOS.
In this work, the composition distribution in SiC films grown on Si(111) using chemical vapor deposition (CVD) method has been measured by the plan-view energy dispersive spectroscopy (EDS). The measuring original EDS data are modified by considering the multilayer structure and the attenuation due to the diffuse reflection at the interface of the voids. The relative error rate of the improved EDS...
Phosphorus transient enhanced diffusion (TED) is caused by interstitial diffusion mechanism. It is important for the efficient suppression of phosphorus diffusion that some carbons could be located on lattice point in the initial stage of re-growth during annealing and trap interstitial Silicon. Carbon co-implantation after Germanium, pre-amorphization implantation (PAI) is applied for the applications...
Polarities of plasma charging damage in n- and p-channel MOSFETs with Hf-based high-k gate stack (HfAlOx/SiO2) were studied for two different plasma sources (Ar-and Cl-based gas mixtures), and found to depend on plasma conditions, in contrast to those with conventional SiO2. For Ar-plasma, which was confirmed to induce a larger charging damage, both n- and p-ch MOSFETs with high-k gate stacks suffer...
To increase memory bandwidth with minimum area overhead, the new concept of 3D-stacked memory structure consisting of a small sense amplifier shared with a few 3D memory cells has been presented. The 16 bit 3D-stacked TiO2 memory chip was fabricated and demonstrated. The estimated bandwidth per unit area of 3D-stacked memory in sub-65 nm CMOS technology indicates that the 3D-stacked memory has potential...
Plasma-exposed Si surface related to Si recess in source/drain region was investigated in detail for various superposed bias configurations with frequencies of 13.56 MHz and 400 kHz. Two different bias powers were utilized by an inductively coupled plasma reactor (ICP). The surface layer (SL) and the interfacial layer between the SL and Si substrate (IL) were analyzed by spectroscopic ellipsometry...
An important driving force behind the microelectronics industry is the ability to pack ever more features onto a silicon chip, by continually miniaturising the individual components. However, after 2015 there is no known technological route to reduce devices below 10 nm. We demonstrate a complete fabrication strategy towards atomic-scale device fabrication in silicon using phosphorus as a dopant in...
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