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In this paper, we have presented a design of hybrid arithmetic logic unit (ALU) in Double precision format (DPF) according to the IEEE-754 standard. In this we have designed an ALU which consists of the two different architectures. First architecture is semi-floating point unit (Semi-FPU) and the second architecture is floating point unit (FPU). Semi-FPU takes a 32-bit integer input and produces an...
Throughout three iterations and six years we have developed a project-based course in HPC for single-box computers tailored to science students in general. The course is based on strong premises: showing that assembly is what actually runs on machines, dividing parallelism in three dimensions (ILP, DLP, TLP), and using them incrementally in a single numerical simulation throughout the course working...
We propose automatic synthesis of application specific instruction set processors (ASIPs). We use pipeline execution of multi-op machine-instructions, e.g., *(reg1*reg2) = (*reg3)+ (*reg4) (C-syntax) an instruction with three memory pipeline stages and two arithmetic stages. The problem is, for a given set of loops, to find a pipeline configuration and a multi-op ISA that maximizes the IPC (instructions...
An iterative, single precision, floating point multiplier is described in this paper, designed and verified using the Verilog description language. The design is provided for educational use, complementing the practical activity in Computer Architecture related courses. The area overhead of the architecture is reduced by resorting to shift-and-add multiplication, allowing to conveniently storing the...
To interact with a computer, a user can walk up to it and interact with it through its local interaction space defined by its input devices. With multiple computers in a room, the user can walk up to each computer and interact with it. However, this can be logistically impractical and forces the user to learn each computers local interaction space. Interaction involving multiple computers also becomes...
In an introductory course of computer architecture, it is of high value that students use a simple and special CPU designed for this purpose and also its graphical simulator for better understanding of the computer hardware operation. In this paper, we present Abu-Reiahn, a simple 8-bit processor which we have specifically designed and built as the introduction part of computer architecture course...
CPU/GPU heterogeneous computing embraces a rapid development in recent years. Considering that there are huge differences between CPU and GPU, CPU/GPU heterogeneous computing still faces many challenges. Therefore, collaborative features of fine-grained and coarse-grained parallelism are necessary to be explored in software designing. This paper takes a comprehensive study both on the CPU/GPU heterogeneous...
This paper advances Linux network computer model based on Loongson Mipsel architecture, from the aspect of computer architecture. This paper develops the target system and Debian/Linux operating system for Loongson network computers, with the thought of software engineering. This paper examines the results of practical operations during implementation phase. Our data demonstrates that Loongson network...
The idea of distributed computer emulation is presented within this paper. Since classic emulation techniques put the power load on the host CPU only, the new approach tries to distribute the load among other available processors within the host platform. The implementation uses OpenCL framework. This standard allows writing high parallel and portable programs in ISO C99 subset language, runnable...
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