The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
Synchronizing clocks is important to guarantee reliable and efficient network functionality for precise coordination among different nodes or components. Clock synchronization becomes more challenging for networks with low-cost devices such as sensors, because these nodes are equipped with unreliable clocks which are vulnerable to noises and environmental changes. With the drastic increase in the...
The structure of an all digital phase-locked loop technology, ADPLL, is proposed in this paper. And the digital phase detector, digital filter loops and digital-controlled oscillators are gradually analyzed. The time order graphs of all modules are presented. In the way of linear approximation, the first-order and second-order mathematic models of ADPLL are given, as well as the control methods. The...
An architecture for a O(1)-loss irreversible n-bit counter is presented in this paper. It is presented as an initial stepping stone application that is suitable for clarifying the potential energy-efficiency advantages of reversible computing. It is based on using fairly standard, irreversible, semi-static CMOS logic. Care is taken to ensure that energy is not dissipated at subsequent counter bits,...
Polymorphic gates can be considered as a new reconfigurable technology capable of integrating logic functions with sensing in a single compact structure. Polymorphic gates whose logic function can be controlled by the level of the power supply voltage (Vdd) represent a special class of polymorphic gates. A new polymorphic NAND/NOR gate controlled by Vdd is presented. This gate was fabricated and utilized...
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.