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A novel RTL countermeasure intended to protect the AddRoundKey step of the AES algorithm against DPA or CPA attacks has been proposed and tested on an AES encoding coprocessor implemented on FPGA. Experimental results based on CPA attacks confirmed the effectiveness of the proposed countermeasure, showing that with 100000 acquired power curves, the absolute value of correlation function is one order...
This paper presents the architecture of a FPGA-based efficient image processing system suited to Wireless Multimedia Sensor Networks. The system consists of two major processing elements: a customized processor for the networking functions and an image processing block. The latter enables the system to detect and extract any updated objects in captured images in real-time. The proposed architecture...
Significant research has demonstrated the performance and power benefits of runtime dynamic reconfiguration of FPGAs and microprocessor/FPGA devices. For dynamically reconfigurable systems, in which the selection of hardware coprocessors to implement within the FPGA is determined at runtime, online estimation methods are needed to evaluate the performance and power consumption impact of the hardware...
Cellular automata (CA) have been accepted as a good evolutionary computational model for the simulation of complex physical systems. They have been used for various applications, such as parallel processing computations and number theory. In this paper, we studied the applications of cellular automata for the modular multiplications; we proposed two new architectures of multipliers based on cellular...
The fast Fourier transform (FFT)is a computationally intensive digital signal processing(DSP)function widely used in applications such as imaging ,software-defined radio, wireless communication, instrumentation and machine inspection. Historically, this has been a relatively difficult function to implement optimally in hardware leading many software designers to use digital signal processors in soft...
The SMILE project attempts to build efficient lowcost clusters based on FPGA boards using their reconfigurability capabilities. A real parallel application of Content-Based Information Retrieval over the SMILE cluster is presented. Using this application the SMILE cluster??s performance is evaluated and compared in terms of time and power consumption with traditional cluster architecture.
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