The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
This work presents an area-efficient voltage and frequency scalable clock generator for low-power digital SoC clocking. Named Direct Digital Sampling and Synthesis (DDSS), the open-loop generator implemented in 28 nm FD-SOI operates from 0.45 V to 1.1V with measured jitter from 1.7% to 5.1% UI. Its low power consumption of 0.40pJ/cycle at 57 MHz 0.5 V combined with the ability to perform fast frequency...
Ensuring accurate testing of a UHF electronic package is the main requirement for a testing system. There are two problems: metrological certification as generator devices generating test pulses of desired amplitude and at a desired moment of time and the problem of measuring amplitude and time parameters of signals at the outputs of an electronic package. This paper observes the methods of measurement...
An all-digital on-chip clock generator is proposed in this paper. It features the tolerance of process, voltage and temperature variation according to the special algorithm. The clock generator depends on CMOS standard delay cell without any external clock source, and the periods of CMOS standard delay cell are calculated by the linear polynomial fitting. The proposed on-chip clock generator has been...
There has recently been interest in diversifying the technologies that provide primary frequency control of the power grid beyond generation. One method of interest to obtain frequency control by turning on or off flexible loads in response to local measurements of line frequency. Because of the large number of loads involved, it is desirable to implement this control without communication among the...
This paper describes a CMOS hysteretic DC-DC buck converter with a low output ripple voltage and a constant switching frequency for mobile applications. The inherent problems of a large output ripple voltage that the conventional hysteretic DC-DC buck converters has faced have been resolved by using the proposed DC-DC buck converter which employed a ramp generator circuit to be able to increase a...
This paper presents an energy-efficient, customizable, high-data-rate, impulse radio ultra wideband (IR-UWB) transceiver, operating in three channels within 3–5GHz for centimeter-to-meter range biotelemetry. Fabricated in 90nm 1P/9M CMOS, the transceiver integrates an all-digital transmitter (TX) with a waveform-synthesis pulse generator and a timing generator for pulse modulation and phase scrambling,...
A fully-digital True Random Number Generator (TRNG) measures the frequency difference between two free-running ring oscillators, or in other words the beat frequency, to extract random frequency jitter. For generating a continuous stream of random bits with a high entropy level, the lower significant bits meeting the NIST randomness criteria are concatenated. The generation efficiency is further improved...
This paper proposes an ultra-low power fully on-chip CMOS relaxation oscillator (ROSC) for a real-time clock application. The circuit has a distinctive feature in compensation architecture of a comparator's non-idealities caused by offset voltage and delay time. The ROSC can generate a stable and higher oscillation clock frequency without increasing power by using a low reference voltage and employing...
This paper introduces a method of using a selected set of the global data for controlling inter-area oscillations of the power network using unified power flow controllers. This novel algorithm utilizes reduced order observers for estimating the missing data the purpose of control when all the data is unavailable through frequency measurements in a wide area control approach. The paper will also address...
A high bandwidth critical path monitor (1 sample/ cycle at 4-5 GHz) capable of providing real-time timing margin information to a variable voltage/frequency scaling control loop is described. The critical path monitor tracks the critical path delay to within 1 FO2 inverter delay with a standard deviation less than 3 FO2 delays over process, voltage, temperature, and workload. The CPM is sensitive...
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.