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This paper presents a temperature and supply compensated sub-threshold voltage reference generator which generates a reference voltage of 173 mV at supply voltage of 0.6 V and temperature @ 27 °C, has been designed in 45 nm CMOS technology. Variation of output voltage with temperature over a range of −25 to 85 °C is 172.88 to 173.25 mV which gives temperature coefficient of 19 ppm/°C at supply voltage...
A voltage reference is introduced in 0.5μm BiCMOS technology in this paper. With curvature compensation, a low offset operational amplifier and a temperature-compensated preregulator, the temperature coefficient of the reference has achieved 5.8ppm/°C from −55°C to 125°C. The preregulator also reduces the power supply dependence of the reference. The reference's PSRR at DC is 92dB.
Two dimensional numerical model of Si-NMOSFET with 0.2 μm gate length is proposed to investigate the effect of heat transfert on the transistor characteristics using comsol simulator. In addition to coupling Poisson and drift diffusion equations, the heat conduction equation is introduced in the numerical model. Temperature distribution due to the heat conduction is investigated. Simulation results...
We propose a control approach to transfer the population between selected quantum states in the non-Markovian open quantum system. This transfers, assisted by single qubit phase shift operations can generate universal logic gates for quantum computing. We find that the occupation probability behaves differently for different environmental conditions, such as the temperature and the ratio between the...
In this work, we develop a statistical thermal simulator including the effect of spatial correlation under within-die process variations. This method utilizes the Karhunen-Loeve (KL) expansion to model the physical parameters, and apply the polynomial Chaoses (PCs) and the stochastic Galerkin method to tackle stochastic heat transfer equations. We demonstrate the accuracy and efficiency of our simulator...
The dramatic increase in leakage current, coupled with the swell in process variability in nano-scaled CMOS technologies, has become a major issue for future IC design. Moreover, due to the spread of leakage power values, leakage variability cannot be neglected anymore. In this work an accurate analytic estimation and modeling methodology has been developed for logic gates leakage under statistical...
Plasma-exposed Si surface related to Si recess in source/drain region was investigated in detail for various superposed bias configurations with frequencies of 13.56 MHz and 400 kHz. Two different bias powers were utilized by an inductively coupled plasma reactor (ICP). The surface layer (SL) and the interfacial layer between the SL and Si substrate (IL) were analyzed by spectroscopic ellipsometry...
Stress sensing test chips are widely utilized to investigate integrated circuit die stresses arising from assembly and packaging operations. In order to utilize these test chips to measure stresses over a wide range of temperatures, one must have values of six piezoresistive coefficients for n- and p-type silicon over the temperature range of interest. However, the literature provides limited data...
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