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A 60 GHz power amplifier (PA) is designed in a 45 nm digital CMOS technology with inductive ESD protection at both RF input and output, and with standard foundry ESD protection for the power pads. Next to state-of-the-art RF performance, a record ESD performance of 5.3 kV HBM and >8.5 A VFTLP is measured, complying with CDM class C4.
Charged device model (CDM) electrostatic discharge (ESD) stress is a major concern for inductor-based ESD protection strategies for RF circuits processed in advanced nano-CMOS technologies. The CDM robustness of such protection methodology is investigated in this paper based on very-fast transmission line pulse (VFTLP) measurements. Its applicability is discussed for future technologies and RF applications.
A 5.5 GHz LNA implemented in 90 nm RF CMOS process is protected against ESD stress using Above-IC inductors implemented as `Plug and Play', which have very high Q values (40 for 3 nH) compared to BEOL inductors (7 for 3 nH in 5 LM). The RF pin of this LNA withstands an ESD stress above 6 kV HBM and 1 kV MM, the highest ESD robustness value reported ever in a similar circuit. The LNA features a 16...
Design and implementation of ESD protection for a 5.5 GHz Low Noise Amplifier (LNA) fabricated in a 90 nm RF CMOS technology is presented. An on-chip inductor, added as ldquoplug-and-playrdquo, is used as ESD protection for the RF pins. The consequences of design and process, as well as the limited freedom on the ESD protection implementation for all pins to be protected are presented in detail and...
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