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This paper proposes a modified hybrid method for the reliability assessment of digital circuits. Such method deals naturally with the occurrence of multiple faults while taking logic masking into account. An extension of the method is proposed so that sequential logic is also supported. The results show that it is in good agreement with other methods in the literature.
Scaling of CMOS technology into nanometric feature sizes has raised concerns for the reliable operation of logic circuits, such as in the presence of soft errors. This paper deals with the analysis of the operation of sequential circuits. As the feedback signals in a sequential circuit can be logically masked by specific combinations of primary inputs, the cumulative effects of soft errors can be...
Reliability analysis of combinational logic circuits using error probabilities methods, such as PTM, has been widely developed and used in literature. However, using these methods for reliability analysis of sequential logic circuits will lead to inaccurate results, because of existence of loops in their architecture. In this paper a new method is proposed based on converting the sequential circuit...
Reliability analysis using error probabilities for combinational logic circuits such as PTM has been investigated widely. Reliability analysis for sequential logic circuits using these methods would be inaccurate because of existence of loops in their architecture. In this paper a new method based on conversion of sequential circuit to combinational one and applying an iterative reliability analysis...
To estimate the reliability and find the weak point of circuits at design phase, several high-level evaluation methods have been proposed recently. However, most of these methods can only be used for combinational circuits. In this paper, we propose a reliability evaluation method based on probabilistic transfer matrices to accurately estimate the reliability of a flip flop circuit. The proposed method...
This paper addresses the problem of logic diagnosis of System-on-Chip (SoC). We propose a diagnosis approach based on a matching algorithm between a set of predicted failures and the set of failures observed during the test phase. The result of the diagnosis is a ranked list of suspected nets able to explain the observed failures. Experimental results show the diagnosis accuracy of the proposed approach...
With technology scaling, radiation-induced soft error has been a major concern even for mainstream enterprise applications. Since various hardening solutions impose significant costs in performance, area and power consumption, full soft error protection can hardly satisfy the multiple design goals simultaneously. Recent studies have noted that the circuits have partial intrinsic immunity to soft errors...
The existence of multiple copies of the same functional units in a design allows on-line testing to be performed by comparing the output responses of identical circuits when identical input sequences are applied to them. We extend the output response comparison scheme for identical sequential circuits in order to increase the fault coverage and reduce the fault latency of an unknown input sequence...
We present a new methodology for fast and accurate simulation of signal probabilities in sequential logic. It can be used for analyzing soft error effects at the logic level, estimating circuit reliability, and the like. Experimental results for large benchmarks show that signal error probabilities can be estimated over many cycles with high accuracy.
Reverse analysis of chip is developed basing on the need of discovering design defection and eliminating hardware security vulnerability, automatic testing and diagnosis of electronic equipments. Nowadays it is the main direction of information security study as well. The data collection which is the key part of the chip reverse analysis is studied in this paper. The completeness of data collection...
Soft errors have been a critical reliability concern in nanoscale integrated circuits, especially in sequential circuits where a latched error can be propagated for multiple clock cycles and affect more than one output, more than once. This paper presents an analytical methodology for enhancing the soft error tolerance of sequential circuits. By using clock skew scheduling, we propose to minimize...
Reactivation noise is an important reliability concern in standard sequential MTCMOS circuits. The ground bouncing noise, the leakage power consumption, and the data stability of various sequential MTCMOS circuits are evaluated in this paper. The attractive application space of different data retention MTCMOS circuit techniques is identified for various design metrics with a 90 nm CMOS technology.
This paper presents an efficient high-level synthesis (HLS) approach to improve RT-level concurrent testing. The proposed method used for both fault detection and fault location. At first the available resources are used in their dead intervals to test active resources for fault detection, and then some changes are applied to the RT-level controller to locate the faults. The fault detection step is...
Timing-error detection and recovery circuits are implemented in a 65 nm resilient circuit test-chip to eliminate the clock frequency guardband from dynamic supply voltage (VCC) and temperature variations as well as to exploit path-activation probabilities for maximizing throughput. Two error-detection sequential (EDS) circuits are introduced to preserve the timing-error detection capability of previous...
Pipelined on-chip interconnects are used in on-chip networks to increase the throughput of interconnects and to achieve freedom in choosing arbitrary network topologies. Since reliability and energy consumption are prominent issues in on-chip networks, they should be carefully considered in the design of pipelined interconnects. In this paper, we propose the use of energy recovery techniques to construct...
Soft errors induced by alpha particles and cosmic radiation have become a highly challenging problem in the design of UDSM or nanoscale circuits, making the incorporation of circuit hardening techniques essential. In this paper, a design technique for soft-error-tolerant sequential elements is presented to improve circuit robustness. The proposed technique exploits time and space redundancy using...
Due to discrepancies in manufacturing process and the probabilistic nature of quantum mechanical phenomenon, nanoelectronic devices cannot be made as reliable as current microelectronic devices. As a result, fault-tolerant architectures are a prerequisite to building reliable electronic systems from these unreliable nanoelectronic devices. One important design aspect of nanoelectronic architecture...
Reliability is a crucial issue in nanoscale devices including both CMOS (beyond 22 nm) and non-CMOS. Devices in this regime tend to be more prone to errors due to thermal effects creating uncertainty in device characteristics. The transient nature of these errors commands the need for a probabilistic model that can represent the inherent circuit logic and can measure the errors. In sequential logic...
Disproportionate instantaneous power dissipation may result in unexpected power supply voltage fluctuations and permanent circuit damage. Therefore, estimation of maximum instantaneous power is crucial for the reliability assessment of VLSI chips. Circuit activity and consequently power dissipation in CMOS circuits are highly input-pattern dependent, making the problem of maximum power estimation...
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