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The limits of technology scaling for smaller chip size, higher performance, and lower power consumption are being reached. For this reason, the memory semiconductor industry is searching for new technology. 3-D stacked memory using through-silicon via (TSV) has been considered as a promising solution for overcoming this challenge. However, to guarantee quality and yield for mass production of 3-D...
Resistive open fault (ROF) represents common manufacturing defects causing extra delays and reliability risks in affected circuits. ROF behavior is sensitive to the supply voltage and the resistance of open (RO). Modeling this fault behavior and detectability with the supply voltage helps in distinguishing between faults as well as testing of multi-voltage designs. While previous ROF models did not...
This paper proposes a realistic low cost fault coverage metric targeting both global and local delay faults. It suggests the test strategy of generating a different number of the longest paths for each line in the circuit while maintaining high fault coverage. This metric has been integrated into the CodGen ATPG tool. Experimental results show significant reductions in test generation time and vector...
Scan chains contain a high percentage of the transistors in logic parts of VLSI designs. Nevertheless, faults inside scan cells are not directly targeted by scan based tests currently used, and they are assumed to be detected by what are called flush tests. Recently we investigated the detectability of stuck-at, stuck-on and stuck-open faults internal to scan chains using existing tests. We also proposed...
The implementation of complex functionality in low-power nano-CMOS technologies leads to enhance susceptibility to parametric disturbances (environmental, and operation-dependent). The purpose of this paper is to present recent improvements on a methodology to exploit power-supply voltage and temperature variations in order to produce fault-tolerant structural solutions. First, the proposed methodology...
The objective of using logic BIST for online and periodic testing is to identify defects, like opens, resulting from the wear and tear of the circuit. We have shown that existing test sets have a low coverage for open defects located in scan flip-flops, even though such defects may affect functional operation. Existing Logic BIST structures suffer from the same limitations. A novel Logic BIST architecture...
Software-based self-test (SBST) has emerged as an effective strategy for non-concurrent on-line testing of processors integrated in embedded system applications. It offers the potential for on-line testing without any hardware overhead. However, test generation is usually based in a semi-automated approach and gate-level information is required for effective test program generation.In this paper we...
This paper describes a methodology for building a reliable internet core router that considers the vulnerability of its electronic components to single event upset (SEU). It begins with a set of meaningful system level metrics that can be related to product reliability requirements. A specification is then defined that can be effectively used during the system architecture, silicon and software design...
In deep submicron era, to prevent larger amount of SRAM from more frequently encountered overheating problems and react accordingly for each possible hotspots, multiple ideal run-time temperature sensors must be closely located and response rapidly to secure system reliability while maintaining core frequency. This paper presented a method to extract run-time temperature information from multiple...
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