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This paper presents an architecture of a hardware network packet generator designed for the COMBOv2 cards using the NetCOPE development platform. The packet generator internal structure allows synthetic IPv4 and IPv6 network packet creation as well as the real network packet transmission. Based on COMBOv2 add-on interface card, the generator is able to transmit packets at speed of 2×10 Gbit/s or 4×1...
This paper describes the behavior of a monolithic DC-DC buck converter's active switch during its on-to-off commutation, under de presence of parasitic inductances due to package pins and bond wires. The parasitic inductances inbuilt in the power supply path cause a voltage spike when commuting the converter current from the active (high side) switch to the passive (low side) switch. This study is...
This paper presents a Current Mode Logic (CML) transmitter circuit that forms part of a Serializer/ Deserializer IP core used in a high speed I/O links targeted for 10+ Gbps Ethernet applications. The paper discusses the 3 tap FIR filter equalization implemented to minimize the effects of Inter Symbol interference (ISI) and attenuation of high speed signal content in the channel. The paper also discusses...
The appearance of layer-3 or upper layer switch, can solve the problems of low forward rate, high delay of traffic that needs to cross networks, so how to implement VLAN-IP in network device with embedded system is a hot problem. This paper introduces layer-3 principle, character and implementation in embedded system.
Access network is the last mile of the network, so there are different access ways. How to effectively recognize the access end station and manage them is the hot pot in research field. This paper discusses a novel auto adaptive access network method and gives the system software structure.
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