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Due to the features of FPGA architectures such as high performance and reconfiguration at run time, they have become remarkable contenders for many mission critical applications, much beyond rapid prototyping only. As the feature size of the semiconductor technology shrinks, also FPGA-based systems using underlying nano-technologies suffer from age-induced parameter deterioration that may finally...
This paper describes a new methodology of construction of the internal activity block of an ICEM-CE model of an FPGA based on a predictive approach using the estimation tools of the dynamic power and the static timing proposed by the manufacturer of the integrated circuit.
This paper presents a novel and simple comb-based decimation nonrecursive structure for the power of three decimation factors. The proposed structure has an improved alias rejection in comparison with the corresponding comb nonrecursive structure. This is achieved by inserting a simple multiplierless filter at the last stage. This filter introduces additional zeros in the certain comb folding bands,...
In the workflow of SKA-SDP (Square Kilometer Array Radio Telescope-Scientific Data Processing), FFT (Fast Fourier Transform) calculation takes a significant proportion of computation overhead. Moreover, FFT computation has to be done within the tight power budget, which existing generic high performance computing architectures cannot meet. To explore power efficiency of FFT computation, this study...
In this paper, we propose new receiver and transmitter architectures to use the Discrete Wavelet Packet Transform (DWPT) and its inverse transform (IDWPT) as a communication medium for wireless body sensor networks. The proposed original transmitter's and receiver's architectures are able to configure the number of sensors due to the considered regular and symmetric structures allowing to modify the...
SRAM is associated with cache memory inside computer system, it increases overall speed of the system. In this work 64kb SRAM is synthesized and simulated on Artix-7 FPGA board by using different Input-Output Standard techniques. For designing SRAM, HSTL_I, HSTL_I_18, HSTL_II and HSTL_II_18 IO Standards are used and power dissipation is calculated on various range of operating frequencies and find...
Power-constrained computing is now becoming essential paradigm in both high performance computing and embedded systems. Power budget is dynamically assigned to each computing resource for improving energy efficiency and system throughput. Modern computer systems have accelerator devices, such as GPUs and FPGAs, for higher energy efficiency and performance. Therefore, power management mechanisms of...
Programmable hardware devices, specifically FPGAs, are increasingly being used in critical applications. State-of-the-art devices use SRAM memory for configuration purposes, which is very sensitive to faults. Previous studies have shown that, the vast majority of the generated errors have a high latency, and that some failures are due to the accumulation of errors. To overcome these threats, manufacturers,...
In this paper, we designed and fabricated a high performance, low power image processing unit for payload camera subsystem for a nano satellite. The nano satellite has very limited power source produced from solar panels as the dimension of this panel is 10×10 cm. The camera system is the most subsystem in the satellite, which consumes high power during the image processing stage. We presented, a...
Recent fixed and mobile wireless communication systems have attracted researchers to propose new techniques and methodologies that greatly improve performance. For example, adaptive techniques have improved the wireless channel efficiency while decreasing the overall power consumption. They consist in reconfiguring parts of the global system automatically according to different parameters. In parallel,...
In this paper, a power analysis of a Nios II processor system is carried out. The methodology of power analysis includes SoPC (System on a Programmable Chip) system integration, architecture design compilation, software program compilation using a toolchain, system simulation and power analysis. In this work, a peak detection algorithm is implemented into the embedded processor system for power analysis...
Requirement of high data rate by the modern mobile communication system requires a linear power amplifier with extremely low power consumption and long battery life. Orthogonal frequency division multiplexing (OFDM) modulation technique promises to deliver high data rate with simple receiver structure. It is more spectral efficient and has been recommended to be used by many standards. But it has...
Many industrial domains rely on vision-based applications which require to comply with severe performance and embedded requirements. Tulipp will develop a reference platform which consists of a hardware system, a tool chain and a real-time operating system. This platform defines implementation rules and interfaces to tackle power consumption issues while delivering high, energy efficient and guaranteed...
We propose a novel FPGA-accelerated BWA-MEM implementation, a popular tool for genomic data mapping. The performance and power-efficiency of the FPGA implementation on the single Xilinx Virtex-7 Alpha Data add-in card is compared against a software-only baseline system. By offloading the Seed Extension phase onto the FPGA, a two-fold speedup in overall application-level performance is achieved and...
Reconfigurability and low power have always been the main concern for the efficient filter implementation. This paper introduces two new low power and high speed reconfigurable Hilbert transformer designs. These designs are based on the carry save adder (CSA) and ripple carry adder (RCA) based row bypassing multipliers. The primary power reduction is procured by turning off adders when the multiplier...
This paper describes the technology-independent approach for FPGA (Field-programmable gate array) and ASIC (Application Specific Integrated Circuit) implementations. This approach is based on the reuse of portable building blocks described at RTL level, thus the design can be mapped to an ASIC or an FPGA devices with few RTL code changes when migrating between FPGA and ASIC. As case study, an OpenRISC...
Digital Front End Reconfiguration is considered one of the most promising techniques to implement the Software Defined Radio (SDR) and the Cognitive Radio (CR), allowing the same set of hardware to accommodate Multi-Standard Communication Systems (MSCS). The benefit increases when the reconfiguration is not only dynamic but also takes place in real time without the need to switch off the system. This...
In this work, we designed a Visitor Counting Machine (VCM) in terms of power efficient circuit using family of three different IO Standards which are LVTTL, Mobile DDR, HSUL 12. These three different IO Standards are compared with each other on the basis of Clock power, Logic power, Signal power, IOs, Leakage power and Total power consumption to search the most power efficient one. In order to find...
This paper elucidates the replicating of a human brain which is energy efficient. The power consumption factor has been highly focused in this research. Attempts have been made to study those conditions at which the consumption of power is minimum. An artificial human brain is advantageous over the real brain due to the fact that it has a higher accuracy, it can perform those rigorous calculation...
This paper contains designing of energy efficient memory circuit using two different IO standard i.e. LVTTL and Mobile-DDR on 28nm (Artix-7) Field Programmable Gate Array. We are using Xilinx ISE simulator version 14.2, Verilog hardware description language and Artix-7 FPGA. The design has been tested at different operating frequencies of Latest Intel processor that are at Intel I-3, Intel I-5 and...
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