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Signed digit representation is vital for implementation of fast arithmetic algorithm and efficient hardware realization. Redundant binary (RB) number representation is the most widely used technique for representation of signed digit number. Again RB representation has ability to provide carry propagation free addition. In this paper we have presented an efficient modified redundant binary (MRB) adder...
As location sensing devices are becoming ubiquitous, overwhelming amounts of data are being produced by the Internet-of-Things-That-Move. Though analyzing this data presents significant business opportunities, new techniques are needed to attain adequate levels of processing performance. One example is the recently introduced geohash geographical coordinate system that is mainly used for indexing...
Stochastic encoding represents a value using the probability of ones in a random bit stream. Computation based on this encoding has good fault-tolerance and low hardware cost. However, one of its major issues is long processing time. We have to use a long enough bit stream to represent a value to guarantee that random fluctuations introduce only small errors to final computation results. For example,...
The paper is concentrated on behavioral and structural specification of reconfigurable logic controllers (RLC). The initial description is given as a hierarchical modular control interpreted Petri net. On the abstract level of the logic synthesis specification is written in propositional sequent language. Rapid modeling and synthesis in FPGA can be done directly from expressions, written in the hardware...
The kernel density estimation (KDE)-based image segmentation algorithm has excellent segmentation performance. However, this algorithm is computational intensive. In addition, although this algorithm can tolerant noise in the input images, such as the noise due to snow, rain, or camera shaking, it is sensitive to the noise from the internal computing circuits, such as the noise due to soft errors...
Problems involving network design can be found in many real world applications such as power systems, vehicle routing, telecommunication networks, phylogenetic trees, among others. These problems involve thousands or millions of input variables and often need information and solution in real time. In general, they are computationally complex (NP-Hard). In this context, metaheuristics like evolutionary...
A neural representation of combinational logic circuit is proposed, called `Logical Neural Network' (LNN). LNN is a feed-forward neural network (NN) where the weights of the network indicate the connections of digital circuit. The logic operations of the circuit such as AND, OR, NOR etc are performed with the neurons of LNN. A modification of Simple Genetic Algorithm (mSGA) is applied to design and...
The following topics are dealt with: image processing; multimedia; VLSI; logic design; pattern recognition; networking; artificial intelligence; soft computing; embedded system; system-on-chip; medical imaging; simulation; modeling; signal processing; communication system; communication network; theme based green communication; signal coding; antenna; mobile communication; wireless communication;...
Logic controller is a digital device used for automation of electromechanical processes, such as control of machinery on factory assembly line or lighting fixtures. This paper presents the method for designing a logic controller. We implement it using reprogrammable structure equipped with Embedded Memory Blocks, e.g. CPLD or FPGA. We find that specification of the controller with appropriate statechart...
Booth algorithm is the classic method of partial product (PP) encoding in hardware design of multiplier, which is adopted by nearly all modern multipliers. This paper carries deep research on the disposal of negative PP based on Radix-4 Booth algorithm. Through recombining PP, it advances a skilled method avoiding the additive arithmetic of “plus 1” when computing the complement for negative PP, without...
This paper presents an optimizing methodology for implementing a multi-layer perceptron (MLP) neural network in a Field Programmable Gate Array (FPGA) device. In order to obtain an efficient implementation, a compromise of time and area is needed. Starting from simulation in the learning phase with fixed point operators, we have developed a methodology which allows the automatic generation of a VHDL...
This paper presents a 32-bit vector multiply-accumulate (MAC) architecture capable of supporting multiple precisions. The vector MAC can perform one 32÷32, one 32÷16, two 16÷16, four 8÷8 bit signed/unsigned multiply-accumulate using Booth encoding algorithm and Wallace tree compressing. A reconfigurable Booth encoding array is implemented using 8÷8 Booth unit as the basic element, and longer bit modes...
For System on-chip (SoC) designs in current Deep Submicron (DSM) era, interconnects play important role in overall performance of the chip. The factors such as propagation delay, power dissipation and crosstalk through RC modeled interconnects substantially affects the entire working of the chip. Functional crosstalk and crosstalk induced propagation delay have recently emerged as major sources of...
Benefit from wave union, the bins (especially the ultra-wide bins) are sub-divided by each other, making FPGA TDC achieve a resolution beyond its cell delay. At such high level resolution, delay chain becomes very sensitive to the environment disturbance, including power supply voltage, temperature and current surge. On chip calibration needs lots of events and hence cannot follow fast delay changes...
This paper introduces a novel Multi-mode Serial Link Controller (MMSLC) for logic physical layer (PHY) and data link layer (DLL) of USB 3.0, PCIe 2.0 and SATA 3.0. Functions defined in these protocols are grouped based on qualifying similarities and workload. The framework consists of a configurable circuit, programmable accelerator and event processor for flexible implementation. This MMSLC can essentially...
There is a critical need for design automation in micro architectural modelling and synthesis. One of the areas which lacks the necessary automation support is synthesis of instruction codes targeting various design optimality criteria. This paper aims to fill this gap by providing a formal method and software tool for synthesis of instruction codes given the description of a processor as a set of...
In this paper, we present several enhancements to power watermarking that allow to simultaneously transmit and verify multiple signatures. Power watermarking of netlist IP cores for FPGA architectures is used for detecting IP fraud where the signature (watermark) is transmitted over the power supply pins of the FPGA. Many (watermarked) IP cores can be combined in an FPGA design, which raises the question...
This paper describes the design of a digital processor targeting the Class-1 Generation-2 EPC Protocol for UHF RFID transponders, and proposes different techniques for reducing its power consumption. The processor has been implemented in a 0.35μm CMOS technology process using automatic tools for both the logic synthesis and layout. Post-layout simulations confirm the fully functionality of the prototype...
To improve noise tolerance of link transmission and router buffers, we propose an error control scheme that integrates a powerful link error recovery method, an efficient buffer error correction coding, and an algorithm to further manage the loss of header and tail flits in a packet. With this method, header and tail flits can be effectively protected, reducing network saturation. Simulation results...
In this paper, we propose a new design method for modulo 2a-1 multipliers which accept double representation of 0 of input operands. The new multiplier takes advantage of the symmetric properties of integers written in l's complement representation which allows to reduce the size of carry-save adders (CSAs) used. Currently, for small a they are the least complex (in terms of the number of logic gates)...
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