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This work demonstrates a new integrated inverse class E amplifier circuit, employing a pHEMT switching device and fully integrated output network for pulse shaping. The circuit is particularly suitable for full integration, since it does not need any RF choke for biasing, and no DC blocking capacitor is needed between the switch and the output network parallel resonance circuit. The back plate capacitances...
This paper describes and compares some of the most energy and area efficient self-calibration techniques reported over the past years. Additional techniques used to further improve power dissipation are briefly described as well. A robust mixed-signal self-calibration technique is proposed, in which, the multi-bit first stage in the ADC is calibrated without requiring any modifications, as long as...
In this paper, an 8-bit (with 5-8bit mode selection), 440-MS/s pipelined Analog-to-Digital Converter (ADC) is presented. The ADC utilizes double-sampling in order to relax the operational amplifier (opamp) settling time requirements. Redundant sign digit (RSD) correction compensates offset errors of the comparators. The ADC is designed with a 0.13-μm CMOS process. In the 8-bit mode, measured effective...
SAR ADCs have been mostly used for moderate-speed, moderate-resolution applications that power consumption is one of the major concerns (e. g. RFID). Furthermore two-step ADCs are classified as high-speed, low to moderate-accuracy ADC. In this paper an ultra low power two-step-SAR ADC for RFID application is presented. Several techniques are used to further reduce the power consumption and relatively...
Here we present the design and implementation of a 130-MHz on-chip reference oscillator in a 0.18-μm 1-ploy 6-metal digital CMOS process. To compensate for the influences on the oscillation frequency by process, supply voltage and temperature (PVT) variations, the oscillator uses a bias adjustment technique without BJT devices, on-chip inductors or external components. Measurements of 8 samples in...
In this paper, an 1-bit second-order low-power ΔΣ modulator for pressure sensor applications is presented. The modulator utilizes correlated double-sampling (CDS) in order to reduce the flicker (1/f) noise. Due to the 1-bit output, the feedback DAC is inherently linear. The modulator is designed with 0.35-μm CMOS process. Measured signal-to-noise and distortion ratio (SNDR) is 86dB (14bits), while...
This paper deals with the design of CMOS sampling switch for ultra-low power analog-to-digital converters (ADC) in biomedical applications. General switch design constraints are analyzed, among which the voltage droop due to the subthreshold leakage current constitutes the major error source for low-speed sampling circuits. Based on the analyses, a CMOS sampling switch with leakage-reduction has been...
This paper presents a conditional capacitor averaging technique to enhance the linearity of 2.5-bit/stage high-resolution pipelined ADCs with capacitor mismatch. Design concepts of capacitor averaging and sorting techniques are employed to mitigate the error effect of capacitor mismatch. Moreover, the sorted capacitors and digital-to-digital converter (DAC) voltages in a 2.5-bit multiplying analog-to-digital...
A low voltage current sensing circuit is presented in this paper. The proposed current sensing circuit performs continuous-tracking with high accuracy over 98% is achieved. The current sensing circuit is implemented with a standard 0.18μm CMOS process at 1.5V supply voltage. The power efficiency obtains 89% over the maximum load current of 540mA. Wide operation frequency range from 400kHz to 25MHz...
The following topics are dealt with: body network application; near-field telemetry; LED driver; MOSFET devices; SRAM circuit; light emitting diode; on-chip reference oscillators; CMOS optical receiver; ring oscillator delay; CMOS inverter; NMOS driver; digital DC-DC converter; low power switched capacitor; low power dual-mode pulse triggered flip-flop; VLSI architecture; and thin film transistor.
A high voltage charge pump design is being presented in this paper. The design is based on Dickson charge pump, constructed with diodes by using AMS 0.35μm technology. The innovation is made in Dickson charge pump i.e. charge control PMOS transistor is used in each stage of charge pump. PMOS transistor is used in series with charging capacitor which reduces the power consumption during the clock transition...
This paper presents the systematic design approach of a low-power, medium-resolution, high-speed pipelined Analog-to-Digital Converter (ADC). The ADC is implemented in 180nm digital CMOS technology. The converter achieves signal-to-noise distortion ratio of 59.8 dB, spurious-free dynamic range of 89 dB and effective number of bits of 9.64-bits at sampling speed of 50MHz with an input signal frequency...
For achieving better linear control in average power, in this paper, a new digital-controlled PWM controller using capacitor integration is proposed. By the integration on a single capacitor, this digital PWM controller can effectively improve the resolution of the conventional counter-based digital PWM but only have a lower clock frequency. Moreover, this proposed digital PWM also can avoid the dynamic...
An analog baseband chain for a Synthetic Aperture Radar (SAR) receiver implemented in a 130nm CMOS technology is presented in this paper. Occupying 0.23mm2 of silicon area, the baseband chain consists of a three-stage Variable Gain Amplifier (VGA), a 5th-order gm-C Low Pass Filter (LPF) and an Output Buffer (OBUF). The gain of the chain can be controlled by tuning the control voltages of the VGA and...
The DC current rejection of a single phase half-bridge grid-connected inverter with a line-frequency isolation transformer is researched in this paper. The impact of the magnetic dc bias of the transformer is given out from the mathematic model of the transformer in current-mode control. For the half-bridge current-mode inverter, the dc current rejection method is presented based on the relationship...
The scheme that the sharp pulse disturbance filter consists of the magnetic core inductor and feed-through capacitor is proposed. The filter is a sort of LC filter where L represents the inductor with a high magnetic permeability core and little distributive capacitance and C represents a feed-through capacitor with little parasitic inductance. Moreover, the method for designing the filter is given...
Nowadays, Sensor network is extensively practical in numerous fields including general engineering, agriculture and environmental monitoring, health monitoring and surgery [1]. Sensors are designed as increasingly efficient and Miniature. As a matter of fact, the most important factor in the design of RF communications is the size of the antenna [2]. In fact, Miniaturization will be subject to steady...
In this paper, we propose a novel versatile engine for behavioral or transistor-level design verification of data converters. This tool is dedicated to IC designers to verify static performance of the converters during their design. It is based on advanced Servo-Loop method presented in and extended by features such as innovative DAC testing method (connecting ADC and DAC testing into one versatile...
This paper deals with the use of the integrated circuit electromagnetic model (ICEM) to analyze, predict, and optimize auto compatibility and electromagnetic emission at PCB level. ICEM is currently under standardization process (IEC62014-3). The basic ICEM architecture is composed of a power distribution network model and an internal current source modeling digital activity. Such an approach enables...
This paper introduces a concept for a reliable and miniaturized power control unit (PCU). With this PCU, an electro-mechanical actuator (EMA) is controlled. This EMA is intended to be used in a swashplateless helicopter control system. As this is a safety relevant part of the helicopter, the PCU needs to work reliably under challenging ambient and operating conditions. At the same time, the whole...
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