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In this paper, the biophysically plausible neuron model i.e. the Hodgkin-Huxley neuron model has been implemented in the field programmable gate arrays (FPGAs) by employing Altera DSP Builder. The action potential generated by Hodgkin-Huxley neurons implemented in FPGA has been compared with the numerical prediction, leading to a good agreement between them. It is believed that this approach could...
Fuzzy logic based inference techniques provide efficient solution for control problems in engineering applications. However due to lack of systematic approaches for hardware implementation of complex fuzzy controllers limits the applicability of these techniques in modern industrial applications. This paper, aims to address various hardware implementation issues of fuzzy system on a reconfigurable...
Jawi is a Malay writing script based on the Arabic script which adds six extra characters to accommodate Malay vocal sounds. Real-Time Speech-To-Text Engine for Jawi Character aims to help students to read Jawi more effectively. In this paper, we investigate the suitable method and device that best for speech-to-text hardware implementation. A complete set of Jawi Speech-To-Text tools will be implements...
This paper use System Generator tool and modular construction methods to build a image algorithm platform in MATLAB R2007a, so as to Implement edge detection of the vehicle pictures. By a brief analysis about display image and resource consumption after achieving on Spartan-3E development board, we can see the image using System Generator for FPGA algorithm design superiority, have the vast application...
Probabilistic neural network (PNN), a kind of radial basis networks, is usually used for classification problems. It has the advantages of much faster training process and more accurate results using the minimum Bayesian risk criterion compared with other neural networks. In this paper, we use this neural network in brain-machine interface for decoding neural ensemble activity. Rats were trained to...
MP3 decoding is usually implemented in the software due to the complexity of its hardware solution. The aim of this work is the hardware implementation of the polyphase filter bank, the most computationally intensive operation in the MP3 decoder, in order to improve the decoder operation speed while saving power. The Altera's Stratix EP1S10F780C6ES FPGA has been used as hardware support taking advantage...
In this paper, a robust, low-complexity timing synchronization algorithm suitable for 5.9 GHz advanced dedicated short range communications (ADSRC) system and its efficient hardware implementation is proposed. Cross-correlation technique is used to detect the starting point of short training symbol and the guard interval of the long training symbol. The design is implemented in a Xilinx Vertex-II...
The proposed poster presents a hardware accelerated left ventricle detection algorithm. Based on marker controlled watershed segmentation method, the algorithm core works sequentially: detection result from a given frame is taken as the segmentation marker to process the next frame. The complete algorithm is written in Matlab. It performs more then 20 elementary operations and needs tens of minutes...
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