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In this paper, a new switching technique for the three-phase multilevel inverter has been presented. The proposed switching technique has been applied to asymmetrical eleven-level inverter. The switching angles have been calculated by using the optimal minimization of total harmonic distortion (OMTHD) technique. The comparison of results with the ordinary switching technique verifies the effectiveness...
Recently, it is required that the high efficiency and small size DC-AC inverter and DC-DC converter are developed for the applications such as solar cells, fuel cells and secondary batteries in the telecommunications, home electronics, industries, electric cars and so forth. A novel bidirectional DC-DC converter is proposed and developed, which realizes the small size and high efficiency 98% is achieved...
With each technology node shrink, a silicon chip becomes more susceptible to soft errors. The susceptibility further increases as the voltage is scaled down to save energy. Based on analysis on cells from commercial libraries, we have quantified the increase in the soft error probability across 65 nm and 45 nm technology nodes at different supply voltages using the Qcrit based simulation methodology...
In this paper, we present a new technique to improve the reliability of H-tree SRAM memories. This technique deals with the SRAM power-bus monitoring by using built-in current sensor (BICS) circuits that detect abnormal current dissipation in the memory power-bus. This abnormal current is the result of a single-event upset (SEU) in the memory and it is generated during the inversion of the state of...
An independent-gate four-terminal FinFET SRAM have been successfully fabricated for drastic leakage current reduction. The new SRAM is consisted of a four-terminal (4T-) FinFET which has a flexible Vth controllability. The 4T-FinFET with a TiN metal gate is fabricated by a newly developed gate separation etching process. By appropriately controlling the Vth of the 4T-FinFET, we have successfully demonstrated...
While the CMOS analog circuits can be designed with the minimum-gate-length of the fabrication process in the alpha-power law MOSFET model, the length of a MOSFET gate has been chosen to be a larger scale than the minimum-gate-length in the conventional Shockleypsilas square model. In this paper, we describe a 6-b 100 MSPS CMOS current steering digital-to-analog converter (DAC) with the alpha-power...
A planar edge termination technique of trenched field limiting ring is investigated by using 2-dimensional numerical analysis and simulation. The better voltage blocking capability and reliability can be obtained by trenching the field-limiting ring site which would be implanted. The trench etch step makes the junction depth deeper so that junction curvature effect and surface breakdown are less happened...
This paper presents an analytical modeling of ballistic and quasi-ballistic transport, implemented in Verilog-A environment and used for circuit simulation. Our model is based on the Lundstrompsilas approach and uses an expression of the backscattering coefficient given by the flux method. The model takes also into account short channel effects and tales into account the effects of different scattering...
BP Solar is involved in long term studies on IV swept, maximum power point tracked or grid connected arrays at currently 67 sites worldwide. Recent studies have shown that many PV arrays can suffer lower performance than expected due mainly to BOS limitations like inverter efficiency, mismatch, shading, thermal losses and V/sub MAX/ tracking accuracy. This paper discusses mathematical methods used...
We assume that long wires represent large capacitive loads, and investigate the effect on the area of a VLSI layout when drivers are introduced along many long wires in the layout. We present a layout for which the introduction of drivers along long wires squares the area of the layout; we show, however, that the increase in area is never greater than this, if the driver can be laid out in a square...
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