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High performance embedded applications are developed using system-on-chips (SoCs) which in turn include silicon intensive, integrated application processors. These SoCs integrate multi-core processor (i.e., ARM Cortex9 or A15) with variety of memory interface controllers, communication interface controllers and special purpose accelerators. Traditionally bus matrix is used for integrating these intellectual...
Leakage power dissipation, timing delay and high noise immunity in advanced embedded static random access memories cells are main critical issues in low power battery operated devices. The newly proposed FinFET based highly noise immune Power gated 6T SRAM design is targeting these areas and successfully suppress leakage power dissipation with maintaining stability of data in standby mode. A single...
A novel low-leakage 8T differential SRAM cell is presented in 65nm bulk CMOS technology with the aim to address standby power consumption of embedded memories. The proposed cell supports differential read and write operation. HSPICE simulations incorporating process variation indicate that the proposed cell exhibits 84.8%, 44.8%, 42.6% and 27.0% less leakage under worst case conditions compared to...
The extent to which the 6T SRAM bit cell can be perpetuated through continued scaling is of enormous technological and economic importance. Understanding the growing limitations in lithography, design and process technology, coupled with the mechanisms which drive systematic mismatch, provides direction in identifying more optimum solutions. We propose an alternative, ultra-thin (UT) SRAM cell layout...
This paper discusses on prospects for area-scaling capabilities of many kinds of SRAM margin assist solutions for VT variability issue, which are based on various efforts by not only the cell topology changes from 6 T to 8 T and 10 T but also incorporating of multiple cell terminal biasing and timing sequence controls of read and write. The various SRAM solutions are analyzed in light of an impact...
The power efficiency of source-coupled logic (SCL) topology for implementing ultra-low-power and low-activity-rate circuits is investigated. It is shown that in low-activity-rate circuits, where the subthreshold leakage consumption of conventional CMOS circuits is more pronounced, subthreshold SCL (STSCL) can be used effectively for reducing the power consumption. An STSCL-based static random-access...
In this paper, we present a new technique to improve the reliability of H-tree SRAM memories. This technique deals with the SRAM power-bus monitoring by using built-in current sensor (BICS) circuits that detect abnormal current dissipation in the memory power-bus. This abnormal current is the result of a single-event upset (SEU) in the memory and it is generated during the inversion of the state of...
This paper compares readout powers and operating frequencies among dual-port SRAMs: an 8T SRAM, 10T single-end SRAM, and 10T differential SRAM. The conventional 8T SRAM has the least transistor count, and is the most area efficient. However, the readout power becomes large and the cycle time increases due to peripheral circuits. The 10T single-end SRAM is our proposed SRAM, in which a dedicated inverter...
Low-cost wireless routers are changing the way people connect to the Internet. They are also very cheap, albeit quite limited, Linux boxes. These attributes make them ideal candidates for wireless mesh routers. This paper presents a minimally invasive mechanism for redundant multipath routing in kernel-space to achieve high reliability with high throughput in a mesh network. This service is essential...
3D contactless technology based on capacitive coupling represents a promising solution for high-speed and low power signaling in vertically integrated chips. AC coupled interconnects do not suffer from mechanical stress, and the parasitic load is much reduced when compared to standard DC solutions, such as wire bonding and micro bumps. Communication system based on wireless interconnection scheme...
In this paper, we propose an adaptive pacing scheme at the link layer for IEEE 802.11 based multihop wireless networks. Our objective is to improve the performance of higher layer protocols without any modifications to them. Our adaptive pacing scheme estimates the four-hop transmission delay in the network path without incurring any additional overheads, and accordingly paces the packets to reduce...
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