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In the minimization of the Mix Polarity Reed-Muller expression (MPRM) circuits, MPRM with different polarities can be got directly from a given Sum-Of-Product expression (SOP). Based on Kronecker Functional Decision Diagrams (KFDDs), a Polarity Conversion Technique (PCT) is proposed. MPRM under a desired polarity is obtained using PCT algorithm, then an Exhaustive-search Technique based on Gray Code...
In this paper, we introduce a new test paradigm called indirect-access scan test, demonstrated over the HOY test platform [12]. Unlike the traditional ATE-based testing, the test data in this paradigm are sent to the chip under test via packets over a single indirect channel. Although there is extra test time overhead for establishing the store-and-forward communication, it offers almost unlimited...
This paper proposes a precise metric of the occurrence of gate logical faults due to manufacturing inaccuracy of the weight and threshold values in threshold logic gates for effective and efficient testing. Based on probability density functions of the values of the manufactured weights and threshold, the probability of gate logical fault occurrence is calculated and used as the metric. The metric...
This paper discusses a test generation method to derive high quality transition tests for combinational circuits. It is known that, for a transition fault, a test set which propagates the errors (late transitions) to all the primary outputs reachable from the fault site can enhance the detectability of unmodeled defects. In this paper, to generate a minimum test set that meets the above property,...
Study on Ion Sensitive Field Effect Transistor (ISFET) based on multi-finger gate design is presented. Mf-ISFET was fabricated by using commercial submicron 1.0 mum CMOS technology and deposited with PECVD Si3N4 as a sensing membrane. The electrical data such as IdVd and IdVg of ISFET are measured to identify the behaviours of ISFET. Furthermore, the evaluation test on ISFET performance such as transient...
We present a generic method for analyzing the effect of process variability in nanoscale circuits. The proposed framework uses kernel and a generic tail probability estimator to eliminate the need for a-priori density choice for the nature of circuit variation. This allows capturing the true nature of the circuit variation from a few random samples of its observed responses. The data-driven, non-parametric,...
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