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Most modern processors have some much faster cache memories than a main memory, and therefore, it is important to effectively utilize it for the efficient execution. The cache memories work well through enhancing temporal or spatial localities in the program. Therefore, the cache efficiency can be improved by making accesses to the same array or structure continuous. We propose the new cache optimization...
Main memory latencies have always been a concern for system performance. Given that reads are on the critical path for CPU progress, reads must be prioritized over writes. However, writes must be eventually processed and they often delay pending reads. In fact, a single channel in the main memory system offers almost no parallelism between reads and writes. This is because a single off-chip memory...
This paper proposes a new circuit design optimization method where Genetic Algorithm (GA) with parameterized uniform crossover (GApuc) is combined with Taguchi method. The purposed are (a) using Taguchi method to search for optimal fitness value and (b) evaluating the power and signal delay of logic blocks in circuit design to get an optimum circuit in complexity, power and signal delay. The present...
Arithmetic blocks consume a major portion of chip area, delay and power. The arithmetic sum-of-product (SOP) is a widely used block. We introduce a novel binary integer linear program (BLP) based algorithm for optimising a general class of mutually exclusive SOPs. Benchmarks drawn from existing literature, standard APIs and constructed for demonstration purposes, exhibit speed improvements of up to...
A total of 7 navigation antennas, have been developed by EADS CASA Espacio within the frame of GSTB-V2 and IOV projects. All these antennas have been fully tested and already delivered, showing very good performance and very repetitive results along the models. Different solutions have been studied in order to improve these performances. Both optimizations (amplitude and geometry) lead to great improvement...
This paper presents and compares different configurations of several heuristic optimization methods with the aim of seeking the one with the best performance when applied to phase synthesis of reflectarray antennas. This phase synthesis is a hard task and improving the synthesis method can result in significant reductions in the associated computational cost. The performance of algorithms such as...
Live multimedia streaming over the Internet has steadily gained popularity over the past decade primarily fueled by the growth in the available network bandwidth and rich multimedia applications. Various approaches to support live multimedia streaming can be broadly categorized into two alternatives, namely, IP multicast based and overlay based. While IP multicast based solution is dependent on the...
Data-flow has proven to be an attractive computation model for programming digital signal processing (DSP) applications. A restricted version of data-flow, termed synchronous data-flow (SDF), offers strong compile-time predictability properties, but has limited expressive power. A new type of hierarchy (Interface-based SDF) has been proposed allowing more expressivity while maintaining its predictability...
This study investigates the relative performances of Array, Wallace, Dadda and Reduced Area multipliers for several synthesis optimization modes. All multiplier designs were modeled in Verilog HDL and synthesized based on the TSMC 0.35-micron ASIC Design Kit standard cell library. Performance data was extracted after logic synthesis in LeonardoSpectrum for Area, Speed and Auto optimization modes....
High-level synthesis is the process of balancing the distribution of RTL components throughout the execution of applications. However, a lot of balancing and optimization opportunities exist below RTL. In this paper, a coarse grain reconfigurable RTL component that combines a multiplier and a number of additions is presented and involved in high-level synthesis. The gate-level synthesis methodology...
An implementation of a radix-4 approximate squaring circuit is described employing a new operand dual recoding technique. Approximate squaring circuits have numerous applications including use in computer graphics, digital radio modules, implementation of division and function approximation in ALU circuits. The theory of operation of the circuit is described including radix-4 operand dual recoding...
Accuracy of speech recognition systems decreases when the distance between talker and microphone increases. By the using of microphone arrays and appropriate filtering of received signals, the accuracy of recognizer can be increased. Many different methods have been proposed. These methods can be classified in two main approaches: Systems that perform in two independent stages of array processing...
Ant colony optimization is being used to solve problems in many scientific fields. In this paper we apply an ant routing algorithm to multi-radio and multi-channel wireless mesh networks. The proposed algorithm introduces ants encountering scheme to imitate the natural process of information sharing between the individuals of an intelligent swarm. Simulation of the routing shows that this new routing...
This paper presents an evaluation of a subband beamforming scheme for speech enhancement and acoustic echo suppression applications, such as hands-free telephony, internet telephony and video conferencing. The aim of the paper is to study the impact of the different types of subband filter banks on the speech enhancement performance. Results show that the octave band filter banks provide an effective...
Using full-custom layouts in 130 nm technology, this work studies how the latency and energy of a checkpointed, CAM-based Register Alias Table (cRAT) vary as a function of the window size, the issue width, and the number of embedded global checkpoints (GCs). These results are compared to those of the SRAM-based RAT (sRAT). Understanding these variations is useful during the early stages of architectural...
Traditionally, spare rows/columns have been used in two ways: either to replace too leaky cells to reduce leakage, or to substitute faulty cells to improve yield. In contrast, we first choose a higher threshold voltage (Vth) and/or gate-oxide thickness (Tox) for SRAM transistors at design time to reduce leakage, and then substitute the resulting too slow cells by spare rows/columns. We show that due...
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