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This paper proposes a FFT processor design for DAB and WiMAX applications whose efficiency is improved in terms of performance. The design is optimized for power. The 2D 256 point FFT employs Radix-16 algorithm which significantly minimizes the number of complex computations. The architecture is pipelined, with 10 bit real and imaginary inputs. The proposed pipelined FFT architecture has the advantage...
This paper shows a novel methodology to reduce the complexity in unrolled CORDIC architectures. The methodology is based on eliminating the CORDIC stages starting from the first stage. As an example, a six stage CORDIC is used but the methodology is applicable on CORDICs with an arbitrary number of stages. The paper shows that the complexity can be reduced by 25%.
In this work efficient architectures of modulo 2n+1 subtractors for diminished-1 operands which can handle zero operand are presented. The proposed subtractors have similar architecture, operate at the same speed and have the same area complexity compared to their corresponding modulo 2n+1 adders for diminished-1 operands. Efficient modulo 2n+1 adder/subtractor architectures for diminished-1 operands,...
The Mellin transform (MT) is a form of a signal representation similar to Fourier transform (FT) which has been widely used in signal processing owing to its distinct properties like scale invariance. In this work, a 2D form of MT which is termed as 2D discrete Mellin transform (DMT) is introduced. The paper also proposes an area efficient, power aware and multiplier less VLSI architecture for 2D...
Computing the inverse of a number in finite fields GF(p) or GF(2n) is equally important for cryptographic applications. A novel scalable and unified architecture for a Montgomery inversion hardware that operates in both GF(p) and GF(2n) is proposed. The scalable design is the novel modification performed on the fixed hardware to make it occupy a small area and operate with better or similar speed,...
In this work we consider structures for simultaneous multiplication by a small set of two pairwise coefficients where the coefficients are the real and imaginary part of a limited number of points uniformly spread on the unit circle. Hence, each such multiplier forms half of a complex multiplier suitable for twiddle factor multiplication in FFT architectures. Based on trigonometric identities we propose...
In this paper, we describe a processor architecture tailored for radix-4 and mixed-radix FFT algorithms, which have lower arithmetic complexity than radix-2 algorithms. The processor is based on transport triggered architecture and several optimizations have been used to improve the energy-efficiency. The processor has been synthesized on a 130 nm standard cell technology and analysis show that a...
The signal processing algorithms face many challenges in real-time applications because of their high computational complexity. Therefore, the major issues have been the enhancement of speed of the arithmetic units in general and multiplications and additions in particular. Double based number systems (DBNS) are increasingly gaining popularity for their capabilities of handling arithmetic operations...
Variable block size motion estimation algorithm is the effcient approach to reduce the temporal redundancies and it has been adopted by the latest video coding standard H.264/AVC. The computational complexity augment coming from the variable block size technique makes the hardwired accelerator essential, especially for real-time applications. In this paper, the authors apply the architecture level...
This paper presents a novel discrepancy computationless RiBM (DcRiBM) algorithm and its architecture for decoding BCH codes. The DcRiBM algorithm allows elimination of the discrepancy computation control block and reduced hardware complexity as compared to conventional RiBM algorithm architecture. The low-complexity DcRiBM architecture has been designed architecture. The low-complexity DcRiBM architecture...
Fast Fourier Transform (FFT) is the most basic and essential part of Software Defined Radio (SDR). Therefore, designing regular, reconfigurable, modular and low hardware complexity FFT computation block is very important. A single FFT block should be configurable for varying length FFT computation and also for computation of different transforms like DCT, DST etc. In this paper, the authors analyze...
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