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The paper describes the mechanism of Agilent 3458A sampling time jitter present when external triggering is used at synchronous two channel sampling. Based on measurements it is shown that the master DMM adds approximately 3.2 ns of its own time jitter while triggering the slave DMM and that the effective time jitter for externally triggered DMM remains at 7 ns, well below ±50 ns maximum jitter as...
Balanced optical-microwave phase detectors (BOMPD) based on fiber Sagnac interferometers and single-ended heterodyne detection are capable of optical-to-RF conversion with sub-femtosecond residual timing jitter. By increasing the BOMPD phase sensitivity and reducing its internal noise down to the thermal noise limit, we achieve an integrated noise floor in the sub-fs regime. Second, we demonstrate...
Nowadays, correlator is a crucial part of communication systems. The correlation function has a great practical importance when it is necessary to process a signal in the presence of noise. Use of correlator in modern communication system have more precise frequency and timing synchronization, which improves its ability against interference of multipath and frequency selective fading channels. Even...
Scale Time Offset Robust Modulation (STORM) is a waveform design technique involving the simultaneous transmission of a base waveform as well as a time-scaled and time-delayed copy of that waveform. For some applications this technique is attractive as a possible candidate to enhance synchronization performance, due to the different tradeoffs of its performance properties. This paper first presents...
Packet-based methods for transporting timing information are becoming increasingly important as networks shift from circuit-switched to packet-switched architectures. The packet-delay variation inherent in packet networks is a primary source of clock noise. This paper addresses suitable methods for analyzing Packet Delay Variation (PDV) and the impact on synchronization. Metrics appropriate for analysis...
We have compared the power supply noise tolerance of a synchronous processor and a self-timed processor fabricated using 0.18mum CMOS. We have designed the self-timed processor using the same RTL as the synchronous processor, and translated it into a netlist with DCVSL circuits and completion logic trees. We have demonstrated the synchronous processor shows an error rate of 9.3% for the worst power...
A 480 Mb/s wireless real-time bus trace system with a pulse-based inductive coupling channel array was developed using a 0.25 mum CMOS digital process. The size and pitch of the inductor array are determined by numerical calculation to optimize the tradeoff between the channel coupling, crosstalk, and alignment tolerance. A low-power quasi-synchronous system is proposed to obtain an enough timing...
This paper presents a new method to use correlator in modern communications after analysing the application and performance of the traditional correlator in detail. According to the results of simulation, the new method have more precise frequency and timing synchronization in wireless communications, which improves its ability against interference of multipath and frequency selective fading. Even...
A critical function required in most all digital communication systems is synchronization. Three levels of synchronization include carrier phase, spreading code timing, and symbol timing estimation. Digital phase phase-locked loops (DPLLs), are often used to implement these functions. Multirate DPLLs are often found in practice where the timing error detector (TED) or phase detector (PD) operates...
A 480 Mb/s wireless real-time bus trace system with a pulse-based inductive coupling channel array was developed using an 0.25 mum CMOS process. The size and pitch of the inductor array are determined by numerical calculation to optimize the tradeoff between the channel coupling, crosstalk, and alignment tolerance. A low-power quasi-synchronous system is proposed to obtain an enough timing margin...
The paper discusses results of dynamic timing analysis of on-die data and clock synchronization in the presence of power supply noise and shows that chip Fmax performance is less sensitive to amount on-die decoupling capacitance Cdie than it has been conventionally expected. The reason is a positive effect of the clock distribution jitter that neutralizes a negative impact of elevated supply noise...
In this paper, we propose a new blind synchronization algorithm for ultra-wideband (UWB) systems based on pseudo random time-hopping (TH) codes. The synchronization parameter is acquired by using integrate-and-dump (I&D) among several segments (these segments are chosen according to a user-specific TH codes) of the observation waveform and peak-picking the outputs of the I&D device. Due to...
In this paper, we adapt four existing timing metrics for frame synchronization in OFDMA mode of WMAN. Among the methods considered, first method uses cyclic prefix information present in the symbol, second method uses the symmetry in the time domain preamble data, third method exploits a priori knowledge of the preamble PN sequence, and the fourth method exploits the conjugate symmetry in the time...
A growing number of applications today are based on the transfer of time and/or frequency over packet networks. This has created a requirement for new methods to support the modeling, testing and implementation of packet based time services. This paper describes a new metric called minTDEV. An overview of the Allan variance family and how this metric fits in is provided. A conceptual and formal definition...
A new simple algorithm for OFDM symbol synchronization is proposed. The proposed algorithm does not assume that the first multipath component is the dominant one. Instead of using a threshold to detect the leading edge of an OFDM symbol, the proposed algorithm uses a metric which is calculated recursively. Two estimation methods are considered, one using the average of the metric results, and the...
A complete channel estimation, synchronization and equalization scheme for a transmitted-reference (TR) ultra-wideband (UWB) system is proposed in this paper. The scheme is based on a data model, which admits moderate data rate and takes all kinds of interference into consideration: between pulses, frames and symbols. Three channel estimators are derived to achieve joint channel and timing estimation,...
The timing acquisition constitutes a major challenge in ultra-wideband impulse radio (UWB-IR). The challenge is not only in detecting pulses with very short duration, but also in considering RMS delay spread caused by multipath channel. This paper presents a novel data-aided synchronization acquisition algorithm. With judiciously designed algorithm and training sequence, the proposed algorithm overcomes...
Aggressive technology scaling tends to reduce integrated circuits resilience against environmental variations. In this paper, we present an adaptive clock buffer circuit design and an adaptive clock distribution network (CDN) to improve chip performance and reliability in the presence of on-chip power-supply variations. The adaptive buffer provides a supply insensitive propagation delay to minimize...
The implementation of complex functionality in low-power nano-CMOS technologies leads to enhance susceptibility to parametric disturbances (environmental, and operation-dependent). The purpose of this paper is to present recent improvements on a methodology to exploit power-supply voltage and temperature variations in order to produce fault-tolerant structural solutions. First, the proposed methodology...
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