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In this paper ultra low power characteristics of the newly proposed energy efficient adiabatic Logic (EEAL) is investigated. EEAL is based on differential cascode voltage swing (DCVS) logic, uses only a single sinusoidal source as supply-clock. With minimal clocking overhead this proposed logic eliminates the floating output problem and enhances the energy efficiency significantly. An EEAL based 8×8...
The isotropic sequence order (ISO) learning is an improved version of differential Hebbian learning algorithm. It uses a switch to turn on or off the learning at appropriate time instants to minimise the level of inherent instability possessed by the classical Hebbian learning. In this paper we present a novel analog very large scale integrated circuit (aVLSI) model to implement ISO learning. The...
This paper presents a new design methodology of the transient voltage clamp (TVC), which operates by controlling inductor current slew rate in 4 switch buck boost converter (4SBB). When 4SBB operates in boost mode, the TVC circuit changes inductor current slew rate during load current step-down to achieve a faster voltage regulation. Due to the slow inductor current slew rate, traditional 4SBB could...
In this paper, the design of biquad polyphase filters with capacitive crosscouplings is presented. Based on the elementary equation s rarr s - jomegac, which describes the frequency shifting, system theoretic modeling is used for design. Some important observations simplifying the design process are denoted. The developed structures have been simulated in Cadence using operational amplifier models...
This paper presents implementation of sequential logic circuits by using a novel quasi-static single-phase adiabatic dynamic logic (SPADL). SPADL uses only a single sinusoidal source as supply-clock which ensures lower energy dissipation and also simplifies the clocking management. Moreover SPADL logic substantially decreases transistor overheads with improved driving ability and circuit robustness...
Present wireless receiver designs often make use of low intermediate frequency structures for signal reception. These topologies frequently apply polyphase filters for noise and image signal attenuation. When using active-RC implementations of single pole or direct synthesis structures, the number of operational amplifiers and thus power consumption becomes high. To confine the latter, a Sallen-Key...
This paper describes the development of a model of vibrating piezoelectric micro-gyro sensor using analog hardware description. Our procedure implies several steps with emphasis in model complexity reduction and identification of critical parameters. The proposed macro-model permits multi-physic simulations including mechanical, piezo-electric and electrical analytic descriptions and allows a top-down...
Previous work have suggested approaches to introduce dynamic element matching (DEM) into the reference net of a flash analog-to-digital converter. No implementations of such circuits have however been reported. In this work the authors evaluate the suitability and estimate the performance enhancements of a recently proposed DEM architecture by using this in the design of a 6-bit Nyquist rate converter...
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