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As fabrication process technology continues to advance, mask set costs have become prohibitively expensive. Structured ASICs can offer price and performance between ASICs and FPGAs. They are attractive for mid-volume production and offer good intellectual property security. In this paper, a structured ASIC methodology, where 2 metal- and 1 via-mask are customised, is described. The CAD tools are fully...
As process geometries shrink, the nonrecurring engineering (NRE) cost is increasing; the ability to make post-fabrication changes to system-on-chip (SoC) is becoming more and more attractive. This ability can be realized by embedding a PLC (programmable logic core) into a SoC. However, the design of PLC is a complex and daunting process; there are many issues to be addressed such as architecture,...
Cellular Automata (CA) are discrete dynamical systems. Physically, a CA consists of consist of a lattice of discrete identical sites called cells, each one taking a value from a finite set. The values of the cells evolve in discrete steps according to deterministic rules that specify the value of the cell in terms of the values of the neighboring sites. Due to its massive parallelism, CA are not appropriated...
This paper introduces an innovative reconfigurable circuit board for rapid system prototyping. This system supports high pin-count packages and high density system integration requirements, and can be programmed to interconnect integrated circuits and other components at near-intra-chip density. This paper presents the concept and investigates several aspects related to its feasibility. Considered...
Advances in technology create both opportunities and challenges in the evolution of the teaching curriculums for Electrical and Computer Engineering programs. This talk will focus on the topics of digital logic, microprocessors, and embedded systems. FPGA technology and the related CAD tools provide new opportunities to evolve these courses so that students obtain more hands-on experience, and learn...
We present a dynamic optimization technique, thread warping, that uses a single processor on a multiprocessor system to dynamically synthesize threads into custom accelerator circuits on FPGAs (field-programmable gate arrays). Building on dynamic synthesis for single-processor single-thread systems, known as warp processing, thread warping improves performances of multiprocessor systems by speeding...
Design methodologies and CAD for "Emotion Engine" LSI are presented with emphasis on practical aspects of verification and timing closure. A combination of simulation, emulation and formal verification ensured the functional first silicon for system evaluation. In order to control wire delay in early design stage, floor plan based synthesis and wire load estimation are adopted for quick...
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