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A 1.25 GS/s 6b ADC is implemented in a 0.13 mum digital CMOS process by time-interleaving two SAR ADCs with 2.5 GHz internal clock frequency that converts 6 bits in 3 cycles. 5.5b ENOB at 1.25 GS/s and 5.8b ENOB at 1 GS/s are achieved without any off-line calibration, error correction or post processing. The entire ADC consumes 32 mW at 1.25 GS/s including T/H and reference buffers, and occupies 0...
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.