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This letter presents an inductor-loaded 2:1 regenerative frequency divider operating up to 331.2 GHz in an InP HBT process, which, to the best of authors' knowledge, is the fastest frequency divider reported thus far. On-wafer measurement shows that the divider is operating from 304.8 GHz to 331.2 GHz, with output power from -27 dBm to -12.3 dBm (no probe loss correction), while dissipating 85.5 mW...
A fully integrated sub-psec jitter PLL realized in a standard digital 0.12µm CMOS copper technology with 1.5V supply is presented. A dual LC-VCO is implemented to support different standards for serial data transmission. We present the general concept and test chip results. Operating with a 311MHz reference clock the PLL achieves typ. 870fs integrated jitter, a phase noise of-115dBc/Hz @1MHz offset,...
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