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A novel technique of fast transient response for frequency control voltage regulator is presented in this paper. For an embedded switched capacitor based DC-DC converter, poor transient response of frequency control voltage regulator is improved with the help of a push-pull dynamic leaker circuit. Push-pull dynamic leaker paths have been used to reduce both peak and dip at the output during load transient...
An all-digital frequency-locked loop (ADFLL) based frequency synthesizer with a built-in FSK modulator for medical implants communication systems (MICS) band applications is presented. The ADFLL uses a high resolution single-bit digital ΣΔ frequency discriminator in the feedback path and a ΣΔ phase accumulator in the reference path, achieving fractional resolution. The ADFLL uses a digital IIR-based...
This paper presents the design of a Direct Digital Frequency Synthesizer (DDFS) circuit based on Dynamic Frequency Management (DFM). In this design, the clock generator circuit dynamically changes its frequency based on the required output frequency. Clock frequency is halved at low output frequencies, to reduce power consumption. Simulations are performed for 0.35 μm and 0.18 μm CMOS process resulting...
Digitally controlled oscillator (DCO) for digital audio broadcasting (DAB) is proposed using 0.18 ??m CMOS process parameters with 1.8 V supply voltage. In this paper, the proposed DCO consist of tri-state inverter array and calibration block. Tri-state inverter array is 5-stage ring oscillator and each stage has 160 tri-state inverters. Calibration block is composed of 64 NMOS pass transistors and...
In this paper, a frequency tunable differential input differential output low noise amplifier (LNA), used for 3-5 GHz OFDM applications, is proposed and analyzed. The LNA has a wideband input matching and a tunable output matching. The digital controlled capacitor arrays in the output matching networks allow the LNA to be switched smoothly in the frequency range of 3 to 5 GHz with output return loss...
A noble automatic frequency calibration (AFC) scheme is proposed for phase-locked loop (PLL) based frequency synthesizer. For fast AFC operation, the frequency control code is updated right after the frequency difference is detected. The uncertainty of the phase relationship between the reference clock and VCO output is eliminated by comparing the divided VCO clock with two-phase reference clocks...
In this paper, a spread spectrum clock generator (SSCG) with a process variation compensator for DisplayPort main link is presented. The process variation compensator not only reduces the error of spread ratio but also guarantees the reliability of the operation of an SSCG against process variation. The proposed SSCG has been implemented in 0.18-mum CMOS process and supports 10-phase 270 MHz and 162...
In this paper, a multi-band delay-locked loop with fast-locked and jitter-bounded features is presented. A programmable charging voltage circuit to the loop filter is developed to accelerate the locking of DLL. The shortest lock time of the proposed DLL is six clock cycles from the unlocked state. In the presented DLL, two phase-frequency detectors with a tunable delay cell are used to reduce the...
A delay-locked loop of multi-band selector with wide-locking range and low power dissipation is presented. The architecture of the proposed delay-locked loop consists of phase frequency detector, charge pump, band selector, multi-control delay line, and start-up circuit. The multi-band selector is used to extend operation frequency of delay-locked loop by switching the multi-control delay line. The...
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