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In this paper, square wave generator using a single second generation differential current conveyor (DCCII) is proposed. The proposed square wave generator consists of two resistors and a single grounded capacitor. CMOS gpdk 180 nm technology was used for designing the proposed circuit. The mathematical analysis, simulation results and experimental results of the proposed circuit are discussed. And...
This paper presents the design and implementation of a embedded processor, xCore_AHB, featuring precise interrupt and exception, which is compatible with ARMv4 architecture. The precise exception mechanism of this design provides not only the quick entrance of the interrupt handle programs but also the interrupt handle programs with the right return address by an additional program counter in write...
This paper introduces a practical system for improving efficiency of low power dc-dc converters regulated by digital voltage-mode PWM controllers. Depending on the input voltage, the controller adaptively changes the switching frequency, thus minimizing related losses while maintaining tight output voltage regulation and constraining electromagnetic interference (EMI) caused by the variable frequency...
System-on-chips (SoCs) are being widely adopted in mobile applications, and are driven by the need for longer battery life, their power budget continues to decrease. In addition, the phase-locked loop (PLL) for the SoC host clock has to be a very low power circuit to support the always-on always-connected (AOAC) feature for SoCs integrated into hand-held devices. The proposed PLL, imple mented in...
This paper presents a capacitor current based adaptive hysteresis controlled DC-DC converter. This controller avoids wide range frequency band filter or complicated compensation. Based on that capacitor current reflects the load current directly and fast, the proposed system uses a simple analog differentiator to sense the voltage capacitor current. Meanwhile, a PI compensation loop is added to improve...
In this paper, a spread spectrum clock generator (SSCG) with a process variation compensator for DisplayPort main link is presented. The process variation compensator not only reduces the error of spread ratio but also guarantees the reliability of the operation of an SSCG against process variation. The proposed SSCG has been implemented in 0.18-mum CMOS process and supports 10-phase 270 MHz and 162...
A function generator circuit using positive type second-generation current-controlled current conveyors [CCCII+]-based voltage mode non inverting band-pass filter (BPF) as a starting building block is proposed. A direct feedback path from the output to the input of the BPF is provided to obtain a sinusoidal oscillator. Then, [CCCII+(2)] of the sinusoidal oscillator is replaced by multioutput current-controlled...
This paper presents principles and results of dynamic testing of an SRAM-based FPGA using time- resolved fault injection with a pulsed laser. The synchronization setup and experimental procedure are detailed. Fault injection results obtained with a DES crypto-core application implemented on a Xilinx Virtex II are discussed.
A delay-locked loop of multi-band selector with wide-locking range and low power dissipation is presented. The architecture of the proposed delay-locked loop consists of phase frequency detector, charge pump, band selector, multi-control delay line, and start-up circuit. The multi-band selector is used to extend operation frequency of delay-locked loop by switching the multi-control delay line. The...
Timing-error detection and recovery circuits are implemented in a 65 nm resilient circuit test-chip to eliminate the clock frequency guardband from dynamic supply voltage (VCC) and temperature variations as well as to exploit path-activation probabilities for maximizing throughput. Two error-detection sequential (EDS) circuits are introduced to preserve the timing-error detection capability of previous...
Class D amplifiers are becoming the most feasible solution for embedded audio application. However, distortions due to the non-linear nature of switching stage are the main drawback for this amplifier topology. This paper discusses the design and implementation of high fidelity audio class D using sliding mode control scheme. This design method proves to be a cost effective solution for industrial...
In order to improve the sinusoidal pulse width modulation (SPWM) control system's real time capability and reduce the system's complexity, a high precision programmable digital three phases SPWM chip based on variable sampling frequency method is designed. The chip can be "programmed" by MCU to set the needed parameters with great flexibility and can be interfaced with multiplexed and non-multiplexed...
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