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Single-event cross sections of four inverter chains, with uniform inverter spacing ranging from 120 nm to 4 μm, were experimentally measured and compared. These inverter chains were irradiated using a focused ion beam. Waveforms of responses were sensed using on-chip wide-bandwidth analog multiplexers. The outputs of the multiplexers drive the 50 Ω inputs of high speed real-time oscilloscopes used...
Single-event upset (SEU) responses of advanced dual- and triple-well planar technologies show significant differences in SEU cross-section for memory cells. The presence of the third well alters the charge-collection mechanism as well as increases the probability of charge sharing, affecting the SEU responses of memory cells. However, at the 16-nm FinFET technology node, heavy-ion experiments show...
Test chips built in a 32 nm bulk CMOS technology consisting of hardened and non-hardened sequential elements have been exposed to neutrons, protons, alpha-particles and heavy ions. The radiation robustness of two types of circuit-level soft error mitigation techniques has been tested: 1) SEUT (Single Event Upset Tolerant), an interlocked, redundant state technique, and 2) a novel hardening technique...
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