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In this paper, we present an approach to analyse the degradation behaviour of the gate dielectric of thousands of MOS transistors simultaneously. Our approach is based on array test structures and automated test systems. The array test structures with a matrix-like arrangement of the MOS devices under test (DUT) have been designed and fabricated in a 130 nm mixed-mode CMOS process. They permit to...
A voltage scalable 0.26 V, 64 kb 8 T SRAM with 512 cells per bitline is implemented in a 130 nm CMOS process. Reverse short channel effect was utilized to improve cell write margin and read performance. A marginal bitline leakage compensation scheme was used during read operation to lower Vmin down to 0.26 V. Floating write bitline and read bitline, auto wordline pulse width control, and a deep sleep...
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