The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
A broadband YIG tuned oscillator (YTO) frequency sweeping signal generator based on the DDS-PLL method is introduced. A linear sweep frequency sinusoidal signal generated by DDS is used to a reference signal of the YTO PLL (Phase-Locked Loop), and the other input of PLL is the linear frequency sweep signal of the YTO, the resulting error correction signal drives the YTO FM coil. Error correction signal...
In this paper a detailed analysis of an UltraWideband correlation receiver is presented. The synchronization methods are discussed and analyzed in terms of practical realizability. All algorithms are implemented on FPGA and tested with a real UWB transceiver. The measurement results are then evaluated and compared to the ones found in the literature. Finally an application example for the correlation...
A new adaptive full digital bit synchronizer, which uses the structure of digital phase-locked loop comprised of lead-lag phase detector and direct digital synthesizer (DDS) is designed based on FPGA. The synchronizer has adaptive characteristic, so the modified quantities of phase can be self adjustment based on difference of the phase. It has also programmable characteristic, so frequency resolution,...
Time synchronization is a key component in numerous wireless sensor network applications. Most of the current software based time synchronization approaches suffer from communication overhead and lack of scalability. In this paper, we propose a hardware based approach based on voltage controlled crystal oscillator and phase locked loop techniques to achieve and maintain sub microsecond level time...
A sine signal synchronous to the power system voltage signal is required in most power electronics based industrial applications. In this study, a phase locked loop (PLL) and direct look-up table (DLT) based hybrid sine oscillator is developed, and sinusoidal signals of the desired frequency that is synchronous to the reference input signal is generated in real time applications carried out with the...
3D contactless technology based on capacitive coupling represents a promising solution for high-speed and low power signaling in vertically integrated chips. AC coupled interconnects do not suffer from mechanical stress, and the parasitic load is much reduced when compared to standard DC solutions, such as wire bonding and micro bumps. Communication system based on wireless interconnection scheme...
A novel 50% duty-cycle corrector (DCC) of digital signal processing (DSP) systems, designed with a purely digital phase-blending technique, is presented in this paper. The novel features of the proposed DCC includes a higher reliability against process, voltage and temperature variation due to the use of the synchronous mirror delay (SMD) technique, no-skew output clock, and a much faster duty-cycle...
A phase detector for timing recovery phase locked loops with an accuracy better than 0.5 % for input frequencies up to 100 MHz is presented. The core of the phase detector consists of two modified Gilbert cells combined so that the offset in their output current is cancelled. This core is expanded with logic circuitry at the input to make the phase detector suitable for timing recovery applications...
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.