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Aging mechanisms such as Bias Temperature Instability (BTI) and Channel Hot Carrier (CHC) are key limiting factors of circuit lifetime in CMOS design. Threshold voltage shift of a device due to degradation is usually a gradual process, only causing moderate increase in failure rate of CMOS designs. Conventional analog and digital circuits typically employ feedback control for system stability or Dynamic...
Process variations and aging effects are proven to have significant impact on paths delay in integrated circuits as technology continues to scale. Identification of the critical paths to test, in a low-cost manner, during both manufacturing and infield tests is thus a challenging task. In this paper, we propose a methodology for identifying testable representative paths (TRPs). The maximum mean delay...
Accurate prediction of circuit aging and its variability is essential to reliable design and analysis. Such a capability further helps reduce the load in statistical reliability test. Based on compact models of transistor degradation and circuit performance, we develop analytical solutions that efficiently predict the statistics of both circuit timing and the leakage under temporal stress and process...
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