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In this paper a new topology for boost converter as well as an efficient control system based on state space modeling is presented in order to improve the power factor of the network. The main objective of this study is to adjust the real power of DG resources connected to network. The proposed power factor correction (PFC) boost converter includes two loops for current and voltage control and on...
Reliability test results of data retention and total ionizing dose (TID) in 65 nm Flash-based field programmable gate array (FPGA) are reviewed. Long-chain inverter design is recommended for reliability evaluation because it can detect degradations of both programmable and erased Flash cells. All the reliability issues are unified and modeled by one natural decay equation.
Usually AC Bias Temperature Instability is modeled as consisting of a recoverable and a permanent component, assuming these components originate from different physical mechanisms. In this work we introduce a model based on charge trapping and detrapping that can properly account for both components. Under switching bias (AC stress), fast traps are able to follow the bias point change, while slow...
In this paper, we present a new technique to improve the reliability of H-tree SRAM memories. This technique deals with the SRAM power-bus monitoring by using built-in current sensor (BICS) circuits that detect abnormal current dissipation in the memory power-bus. This abnormal current is the result of a single-event upset (SEU) in the memory and it is generated during the inversion of the state of...
Various switch designs for the hybrid redundancy scheme are studied. A reliability model for the switch is developed and the switch is shown to be a significant factor in the overall system reliability. A hybrid redundancy scheme with a triple-modular redundant (TMR) core may have a maximum attainable reliability for only a spare or two. Adding spares complicates the switch enough to cause the system...
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